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FALC
56
PEF 2256 H/E
Signaling Controller Operating Modes
User’s Manual
Hardware Description
215
DS1.1, 2003-10-23
8.3
Signaling Controller Functions
8.3.1
Transparent Transmission and Reception
When programmed in the extended transparent mode via the MODE registers
(MODE.MDS(2:0) = 111, MODE2.MDS2(2:0)=111, MODE3.MDS3(2:0)=111), the
FALC
56 performs fully transparent data transmission and reception without HDLC
framing, i.e. without
Flag insertion and deletion
CRC generation and checking
Bit stuffing
In order to enable fully transparent data transfer, bit MODE.HRAC (MODE2.HRAC2,
MODE3.HRAC3) has to be set.
Received data is always shifted into RFIFO (RFIFO2, RFIFO3).
Data transmission is always performed out of XFIFO (XFIFO2, XFIFO3) by shifting the
contents of XFIFO into the outgoing data stream directly. Transmission is initiated by
setting CMDR.XTF (04
H
). A synchronization byte FF
H
is sent automatically before the
first byte of the XFIFO is transmitted.
Cyclic Transmission (fully transparent)
If the extended transparent mode is selected, the FALC
56 supports the continuous
transmission of the contents of the transmit FIFOs.
After having written 1 to 32 bytes to XFIFO (XFIFO2, XFIFO3), the command
XREP&XTF (CMDR = 00100100 = 24
H
) forces the FALC
56 to transmit the data stored
in XFIFO to the remote end repeatedly.
Note: The cyclic transmission continues until a reset command (CMDR.SRES) is issued
or with resetting of CMDR.XREP, after which continuous “1”s are transmitted.
During cyclic transmission the XREP-bit has to be set with every write operation
to CMDR.
The same handling applies to CMDR2 and CMDR3 for HDLC channels 2 an 3.
8.3.2
CRC on/off Features
As an option in HDLC mode the internal handling of the received and transmitted CRC
checksum can be influenced via control bits CCR2.RCRC and CCR2.XCRC (channel 2:
CCR3.RCRC2, CCR3.XCRC2, channel 3: CCR4.RCRC3, CCR4.XCRC3).
Receive Direction
The received CRC checksum is always assumed to be in the 2 last bytes of a frame
(CRC-ITU), immediately preceding a closing flag. If CCR2.RCRC is set, the received
CRC checksum is written to RFIFO where it precedes the frame status byte (contents of
register RSIS). The received CRC checksum is additionally checked for correctness. If