FALC
56
PEF 2256 H/E
T1/J1 Registers
User’s Manual
Hardware Description
361
DS1.1, 2003-10-23
00 = NRZ (optical interface)
01 = CMI (1T2B+B8ZS), (optical interface)
10 = AMI coding with Zero Code Suppression (ZCS, B7-stuffing),
(ternary or digital dual-rail interface)
11 = B8ZS Code (ternary or digital dual-rail interface)
After changing RC(1:0), a receiver software reset is required
(CMDR.RRES = 1).
FRS
Force Resynchronization
A transition from low to high forces the frame aligner to execute a
resynchronization of the pulse frame. In the asynchronous state, a
new frame position is assumed at the next candidate if there is one.
Otherwise, a new frame search with the meaning of a general reset is
started. In the synchronous state this bit has the same meaning as bit
FMR0.EXLS except if FMR2.MCSP = 1.
SRAF
Select Remote (Yellow) Alarm Format for F12 and ESF Format
0 =
F12: bit2 = 0 in every channel. ESF: pattern
“1111 1111 0000 0000” in data link channel.
1 =
F12: FS-bit of frame 12. ESF: bit2 = 0 in every channel
EXLS
External Loss Of Frame
With a low to high transition a new frame search is started. This has
the meaning of a general reset of the internal frame alignment unit.
Synchronous state is reached only if there is one definite framing
candidate. In the case of multiple candidates, the setting of the bit
FMR0.FRS forces the receiver to lock onto the next available framing
position.
SIM
Alarm Simulation
Setting/resetting this bit initiates internal error simulation of: AIS (blue
alarm), loss-of-signal (red alarm), loss of frame alignment, remote
(yellow) alarm, slip, framing errors, CRC errors, code violations. The
error counters FEC, CVC, CEC, EBC are incremented.
The selection of simulated alarms is done by the error simulation
counter: FRS2.ESC(2:0) which is incremented with each setting of bit
FMR0.SIM. For complete checking of the alarm indications eight
simulation steps are necessary (FRS2.ESC(2:0) = 0 after a complete
simulation).
SIM has to be held stable at high or low level for at least one receive
clock period before changing it again.