FALC
56
PEF 2256 H/E
E1 Registers
User’s Manual
Hardware Description
268
DS1.1, 2003-10-23
RESX
Rising Edge Synchronous Pulse Transmit
Depending on this bit all transmit system interface data and marker
are clocked or sampled with the selected active edge.
CMR2.IXSC = 0:
0
latched with the first falling edge of the selected PCM highway
clock.
1
latched with the first rising edge of the selected PCM highway
clock.
CMR2.IXSC = 1:
The value of RESX bit has no impact on the selected edge of the PCM
highway clock but value of RESR bit is used as RESX.
Example: If RESR = 0, the rising edge of PCM highway clock is the
selected one for sampling data on XDI and vice versa.
RESR
Rising Edge Synchronous Pulse Receive
Depending on this bit all receive system interface data and marker are
clocked with the selected active edge.
0 =
Latched with the first falling edge of the selected PCM highway
clock.
1 =
Latched with the first rising edge of the selected PCM highway
clock.
Note: If bit CMR2.IRSP is set, the behavior of signal RFM (if used) is
inverse (1 = falling edge, 0 = rising edge)
TTRF
TTR Register Function (Fractional E1 Access)
Setting this bit the function of the TTR(4:1) registers is changed. A
one in each TTR register forces the XSIGM marker high for the
corresponding time slot and controls sampling of the time slots
provided on pin XSIG. XSIG is selected by PC(4:1).XPC(3:0).
DAF
Disable Automatic Freeze
0 =
Signaling is automatically frozen if one of the following alarms
occurred: Loss-Of-Signal (FRS0.LOS), Loss of CAS Frame
Alignment (FRS1.TS16LFA), or receive slips (ISR3.RSP/N).
1 =
Automatic freezing of signaling data is disabled. Updating of the
signaling buffer is also done if one of the above described alarm
conditions is active. However, updating of the signaling buffer
is stopped if SIC2.FFS is set. Significant only if the serial
signaling access is enabled.