FALC
56
PEF 2256 H/E
Functional Description E1
User’s Manual
Hardware Description
81
DS1.1, 2003-10-23
Because the CAS controller is working on the PCM highway side of the receive buffer,
slips disturb the CAS data.
Figure 24
2.048 MHz Receive Signaling Highway (E1)
4.1.15.5
Channel Associated Signaling CAS (E1, μP access mode)
The signaling information is carried in time slot 16 (TS16). Receive data is stored in
registers RS(16:1) aligned to the CAS multiframe boundary. The signaling controller
samples the bit stream either on the receive line side or if external signaling is enabled
on the receive system side.
The signaling procedure is done as it is described in ITU-T G.704 and G.732.
The main functions are:
Synchronization to a CAS multiframe
Detection of AIS and remote alarm in CAS multiframes
Separation of CAS service bits X1 to X3
Storing of received signaling data in registers RS(16:1) with last look capability
Updating of the received signaling information is controlled by the freeze signaling
status. The freeze signaling status is automatically activated if a loss-of-signal
(FRS0.LOS = 1), or a loss of CAS multiframe alignment (FRS1.TSL16LFA = 1) or a
receive slip occurs. The current freeze status is output on port FREEZE (RP(A:D)) and
indicated by register SIS.SFS. Optionally automatic freeze signaling can be disabled by
setting bit SIC3.DAF. If SIS.SFS is active, updating of the registers RS(16:1) is disabled.
To relieve the μP load from always reading the complete RS(16:1) buffer every 2 ms the
FALC
56 notifies the μP through interrupt ISR0.CASC only when signaling changes
F0133
A B C D
A B C D
4 5 6 7
0 1 2 3 4 5 6 7
TS31
TS0
TS1
0 0 0 0 X Y X X
0 1 2 3 4 5 6 7
TS16
A B C D
0 1 2 3 4 5 6 7
TS31
RSIG
RDO
SCLKR
FAS/NFAS
FAS/NFAS
SYPR
T
125 μs
T
FAS
NFAS
ABCD
0000XYXX
= Time slot offset (RC0, RC1)
= Frame alignment signal
= TS0 not containing FAS
= Signaling bits for time slots 1...15 and 17...31 of CAS multiframe
= CAS multiframe alignment signal in TS16