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| 型号： | PEF3452 |
| 厂商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Line Interface Unit for DS3, STS 1 and E3 |
| 中文描述： | 线路接口单元的DS3中，STS 1和E3 |
| 文件页数： | 34/71页 |
| 文件大小： | 1372K |
| 代理商： | PEF3452 |
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PEF 3452
TE3-LIU V1.3
Interface Description
Preliminary Data Sheet
24
2001-12-05
PRELIMINARY
4.1.4
Receive Clock and Data Recovery
The receive clock and data recovery extracts the route clock RCLK from the digital data
stream and converts the data stream into a dual rail bit stream. The clock and data
recovery needs a reference clock to keep the PLL stable during times without data signal
at RL1/RL2. The clock that is output on pin RCLK is the recovered clock of the signal
provided on RL1/RL2 and has a duty cycle close to 50
%
. The intrinsic jitter generated
in the absence of any input jitter is defined in
Chapter 4.1.8
. The PLL reference clock is
generated internally without the need for external components.
4.1.5
Receive Line Coding
In E3 applications the HDB3 and the AMI coding is provided for the data received from
the ternary interface. In DS3/STS-1 mode the B3ZS and AMI code is supported. In B3ZS
or AMI code all code violations are detected and indicated.
4.1.5.1
AMI Code
The AMI code is defined as a dual rail data signal, where the combinations 00 (
"
0
"
), 10
(
"+
1
"
) and 01 (
"
-1
"
) are valid. No subsequent
"+
1
"
or
"
-1
"
bits are allowed, these will be
detected as bipolar violations and indicated on pin RDON/BPV, if single rail mode is
selected (according to ANSI T1.231 chapter 7.1).
The received AMI data stream is either switched transparently to the framer interface as
dual rail data or converted into a single rail data stream.
4.1.5.2
B
3
Z
S Code
In the B3ZS line code each block of three consecutive zeros is replaced by either of two
replacements codes which are B0V and 00V, where B represents a pulse which applies
to the bipolar rule (
"+
1
"
or
"
-1
"
) and V represents a bipolar violation (two consecutive
"+
1
"
or
"
-1
"
bits). The replacement code is chosen in a way that there is an odd number of
valid B pulses between consecutive V pulses to avoid the introduction of a DC
component into the analog signal.
The receive line decoder decodes the incoming B3ZS data signal and changes the
replacement patterns to the original three-zeros pattern. Pattern sequences violation
these rules are reported as bipolar violation errors.
Data output to the framer interface can be selected to be either dual rail or single rail.
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参数描述 |
|---|---|
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