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参数资料
| 型号： | PF48F4P0ZT00 |
| 厂商： | Intel Corp. |
| 元件分类： | 圆形连接器 |
| 英文描述： | Circular Connector; No. of Contacts:21; Series:; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:22; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:22-21 |
| 中文描述： | 英特尔StrataFlash嵌入式存储器 |
| 文件页数： | 64/102页 |
| 文件大小： | 1609K |
| 代理商： | PF48F4P0ZT00 |
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1-Gbit P30 Family
April 2005
64
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet
11.3.1
BEFP Requirements and Considerations
BEFP requirements:
Case temperature: T
C
= 25
°C
± 5
°C
V
CC
within specified operating range
VPP driven to V
PPH
Target block unlocked before issuing the BEFP Setup and Confirm commands
The first-word address (WA0) for the block to be programmed must be held constant from the
setup phase through all data streaming into the target block, until transition to the exit phase is
desired
WA0 must align with the start of an array buffer boundary
1
BEFP considerations:
For optimum performance, cycling must be limited below 100 erase cycles per block
2
BEFP programs one block at a time; all buffer data must fall within a single block
3
BEFP cannot be suspended
Programming to the flash memory array can occur only when the buffer is full
4
NOTES:
1.
Word buffer boundaries in the array are determined by A[4:0] (0x00 through 0x1F). The alignment start
point is A[4:0] = 0x00.
2.
Some degradation in performance may occur if this limit is exceeded, but the internal algorithm
continues to work properly.
3.
If the internal address counter increments beyond the block's maximum address, addressing wraps
around to the beginning of the block.
4.
If the number of words is less than 32, remaining locations must be filled with 0xFFFF.
11.3.2
BEFP Setup Phase
After receiving the BEFP Setup and Confirm command sequence, Status Register bit SR[7]
(Ready) is cleared, indicating that the WSM is busy with BEFP algorithm startup. A delay before
checking SR[7] is required to allow the WSM enough time to perform all of its setups and checks
(Block-Lock status, V
PP
level, etc.). If an error is detected, SR[4] is set and BEFP operation
terminates. If the block was found to be locked, SR[1] is also set. SR[3] is set if the error occurred
due to an incorrect V
PP
level.
Note:
Reading from the device after the BEFP Setup and Confirm command sequence outputs Status
Register data. Do not issue the Read Status Register command; it will be interpreted as data to be
loaded into the buffer.
11.3.3
BEFP Program/Verify Phase
After the BEFP Setup Phase has completed, the host programming system must check SR[7,0] to
determine the availability of the write buffer for data streaming. SR[7] cleared indicates the device
is busy and the BEFP program/verify phase is activated. SR[0] indicates the write buffer is
available.
相关PDF资料 |
PDF描述 |
|---|---|
| PF48F2000P0ZBQ0 | Intel StrataFlash Embedded Memory |
| PF48F3000P0ZBQ0 | CAP 0.01UF 63V 10% MET-POLY-BOX RAD5MM 7.5X6.5X2.5MM BULK |
| PF48F4000P0ZBQ0 | Intel StrataFlash Embedded Memory |
| PF48F0P0ZBQ0 | Intel StrataFlash Embedded Memory |
| PF48F2P0ZBQ0 | Intel StrataFlash Embedded Memory |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PF48F4P0ZTQ0 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| PF48F5000M0Y1BEA | 制造商:Micron Technology Inc 功能描述:512BA/0S SCSP 1.8 X16D HF B1 ADMUX - Trays |
| PF48F6000M0Y0BEA | 制造商:Micron Technology Inc 功能描述:1024CP/0CP SCSP 1.8 X16D LF - Trays |
| PF48F6000M0Y0BHA | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays |
| PF48F6000M0Y1BHA | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays |
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