参数资料
型号: PI74SSTU32866NBE
厂商: Pericom
文件页数: 15/18页
文件大小: 0K
描述: IC 25BIT CONFIG REG BUFF 96LFBGA
产品变化通告: Product Discontinuation Notice 22/Jan/2010
标准包装: 285
逻辑类型: 带奇偶位的可配置寄存缓冲器
位数: 25
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 96-LFBGA
供应商设备封装: 96-LFBGA(13.5x5.5)
包装: 托盘
6
PS8739B
11/21/05
PI74SSTU32866
25-bit 1:1 or 14-bit 1:2 Configurable
Registered Buffer with Parity
Function Table (each flip flop)
Inputs
Outputs
RST
DCS
CSR
CK
Dn, DODT,
DCKE
Qn
QCS
QODT,
QCKE
H
L
L
H
L
H
L
H
L
L or H
X
Q0
H
L
H
L
H
L
H
H
L
H
L
H
L or H
X
Q0
H
L
L
H
L
H
L
H
L
L or H
X
Q0
H
L
Q0
H
L
H
H
Q0
H
L or H
X
Q0
L
X or floating X or floating X or floating X or floating X or floating
L
Inputs
Outputs
RST
DCS
CSR
CK
∑ of inputs = H
(D1- D25)(7)
PAR_IN(8)
PPO
QERR(9)
H
L
X
Even
L
H
L
X
Odd
L
H
L
H
L
X
Even
H
L
H
L
X
Odd
H
L
H
L
Even
L
H
L
Odd
L
H
L
H
L
Even
H
L
H
L
Odd
H
L
H
X
PPO0
QERR0
H
X
L or H
X
PPO0
QERR0
L
X or floating X or floating X or float-
ing
X or float-
ing
X or floating
X or float-
ing
L
H
Notes:
7.
Data inputs = D2, D3, D5, D6, D8-D25 when C0=0 and C1=0
Data inputs = D2, D3, D5, D6, D8-D14 when C0=0 and C1=1
Data inputs = D1-D6, D8-D10, D12, D13 when C0=1 and C1=1
8.
PAR_IN arrives one clock cycle (C0=0), or two clock cycles (C0=1), after the data to which it applies
9.
this transition assumes QERR is high at the crossing of CK going high and CK going low. If QERR is low, it stays latched low for two
clock cycles or until RST is driven low
Function Table (Parity and Stand-by)
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