参数资料
型号: PIC14000-04I/SO
厂商: Microchip Technology
文件页数: 97/153页
文件大小: 0K
描述: IC MCU OTP 4KX14 A/D 28SOIC
产品培训模块: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
标准包装: 27
系列: PIC® 14
核心处理器: PIC
芯体尺寸: 8-位
速度: 4MHz
连通性: I²C
外围设备: POR,温度传感器,WDT
输入/输出数: 20
程序存储器容量: 7KB(4K x 14)
程序存储器类型: OTP
RAM 容量: 192 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 6 V
数据转换器: 斜率 A/D
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
包装: 管件
配用: ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING
309-1073-ND - ADAPTER 28-SOIC TO 28-SOIC
309-1024-ND - ADAPTER 28-SOIC TO 28-DIP
309-1023-ND - ADAPTER 28-SOIC TO 28-DIP
PIC14000
DS40122B-page 48
Preliminary
1996 Microchip Technology Inc.
FIGURE 7-13:
I2C BLOCK DIAGRAM
Read
Write
Internal
data bus
RC7/SDAA
I2CSR
I2CBUF
MSB
Match Detect
Start and
RC6/SCLA
I2CADD
Stop bit detect
Addr_Match
Set, Reset
S, P bits
(I2CSTAT Reg)
Shift
clock
RD1/SDAB
RD0/SCLB
4:2
MUX
SCK
SDA
MISC<4>
7.5
I2C Operation
The I2C module in I2C mode fully implements all slave
functions, and provides support in hardware to facilitate
software implementations of the master functions. The
I2C module implements the standard and fast mode
specications as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the
RC6/SCLA pin, which is the I2C clock, and the
RC7/SDAA pin which acts as the I2C data. The I2C
module can also be accessed via the RD0/SCLB and
RD1/SDAB pins by setting I2CSEL (MISC<4>).The
user must congure these pins as inputs or outputs
through the TRISC<7:6> or TRISD<1:0> bits. A block
diagram of the I2C module in I2C mode is shown in
Figure 7-13. The I2C module functions are enabled by
setting the I2CCON<5> bit.
The I2C module has ve registers for I2C operation.
These are the:
I2C Control Register (I2CCON)
I2C Status Register (I2CSTAT)
Serial Receive/Transmit Buffer (I2CBUF)
I2C Shift Register (I2CSR) - Not directly
accessible
Address Register (I2CADD)
The I2CCON register (14h) allows control of the I2C
operation. Four mode selection bits (I2CCON<3:0>)
allow one of the following I2C modes to be selected:
I2C Slave mode (7-bit address)
I2C Slave mode (10-bit address)
I2C Slave mode (7-bit address), with start and
stop bit interrupts enabled
I2C Slave mode (10-bit address), with start and
stop bit interrupts enabled
I2C Firmware Controlled Master mode, slave is
idle
Selection of any I2C mode with the I2CEN bit set, forces
the SCL and SDA pins to be open collector, provided
these pins are set to inputs through the TRISC bits.
The I2CSTAT register gives the status of the data
transfer. This information includes detection of a
START or STOP bit, species if the received byte was
data or address, if the next byte is the completion of
10-bit address, and if this will be a read or write data
transfer. The I2CSTAT register is read only.
The I2CBUF is the register to which transfer data is
written to or read from. The I2CSR register shifts the
data in or out of the device. In receive operations, the
I2CBUF and I2CSR create a double buffered receiver.
This allows reception of the next byte before reading
the last byte of received data. When the complete byte
is received, it is transferred to the I2CBUF and PIR1<3>
is set. If another complete byte is received before the
I2CBUF is read, a receiver overow has occurred and
the I2CCON<6> is set.
The I2CADD register holds the slave address. In 10-bit
mode, the user needs to write the high byte of the
address (1 1 1 1 0 A9 A8 0). Following the high byte
address match, the low byte of the address needs to be
loaded (A7-A0).
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