参数资料
型号: PIC16C433/JW
厂商: Microchip Technology
文件页数: 11/126页
文件大小: 0K
描述: IC MCU 2KX14 LIN TXRX 18CDIP
标准包装: 25
系列: PIC® 16C
核心处理器: PIC
芯体尺寸: 8-位
速度: 10MHz
连通性: LIN(本地互连网络)
外围设备: POR,WDT
输入/输出数: 5
程序存储器容量: 3.5KB(2K x 14)
程序存储器类型: EPROM,UV
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 4.5 V ~ 5.5 V
数据转换器: A/D 4x8b
振荡器型: 内部
工作温度: 0°C ~ 70°C
封装/外壳: 18-CDIP(0.300",7.62mm)窗口
包装: 管件
产品目录页面: 636 (CN2011-ZH PDF)
配用: DVA16XP185-ND - ADAPTER DEVICE ICE 18DIP/SOIC
108
4378C–AVR–09/08
AT90PWM1
put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes
the COMnx1:0 bits control whether the output should be set, cleared or toggle at a compare
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 115.
15.8.1
Normal Mode
The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the
BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOVn) will be set in
the same timer clock cycle as the TCNTn becomes zero. The TOVn Flag in this case behaves
like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow
interrupt that automatically clears the TOVn Flag, the timer resolution can be increased by soft-
ware. There are no special cases to consider in the Normal mode, a new counter value can be
written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maximum
interval between the external events must not exceed the resolution of the counter. If the interval
between events are too long, the timer overflow interrupt or the prescaler must be used to
extend the resolution for the capture unit.
The Output Compare units can be used to generate interrupts at some given time. Using the
Output Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
15.8.2
Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGMn3:0 = 4 or 12), the OCRnA or ICRn Register
are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when
the counter value (TCNTn) matches either the OCRnA (WGMn3:0 = 4) or the ICRn (WGMn3:0 =
12). The OCRnA or ICRn define the top value for the counter, hence also its resolution. This
mode allows greater control of the compare match output frequency. It also simplifies the opera-
tion of counting external events.
The timing diagram for the CTC mode is shown in Figure 15-6. The counter value (TCNTn)
increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn)
is cleared.
Figure 15-6. CTC Mode, Timing Diagram
An interrupt can be generated at each time the counter value reaches the TOP value by either
using the OCFnA or ICFn Flag according to the register used to define the TOP value. If the
TCNTn
OCnA
(Toggle)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1
4
Period
2
3
(COMnA1:0 = 1)
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