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| 型号： | PIC16C620A-04/P301 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDIP18 |
| 封装： | 0.300 INCH, PLASTIC, DIP-18 |
| 文件页数： | 61/108页 |
| 文件大小： | 674K |
| 代理商： | PIC16C620A-04/P301 |
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PIC16C62X
DS30235G-page 56
Preliminary
1998 Microchip Technology Inc.
9.5.1
RB0/INT INTERRUPT
External interrupt on RB0/INT pin is edge triggered:
either rising if INTEDG bit (OPTION<6>) is set, or fall-
ing, if INTEDG bit is clear. When a valid edge appears
on the RB0/INT pin, the INTF bit (INTCON<1>) is set.
This interrupt can be disabled by clearing the INTE
control bit (INTCON<4>). The INTF bit must be cleared
in software in the interrupt service routine before
re-enabling this interrupt. The RB0/INT interrupt can
wake-up the processor from SLEEP, if the INTE bit was
set prior to going into SLEEP. The status of the GIE bit
decides whether or not the processor branches to the
interrupt vector following wake-up. See Section 9.8 for
details on SLEEP and Figure 9-18 for timing of
wake-up from SLEEP through RB0/INT interrupt.
9.5.2
TMR0 INTERRUPT
An overow (FFh
→ 00h) in the TMR0 register will
set the T0IF (INTCON<2>) bit. The interrupt can
be
enabled/disabled
by
setting/clearing
T0IE
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 6.0.
9.5.3
PORTB INTERRUPT
An input change on PORTB <7:4> sets the RBIF
(INTCON<0>) bit. The interrupt can be enabled/dis-
abled by setting/clearing the RBIE (INTCON<4>) bit.
For operation of PORTB (Section 5.2).
9.5.4
COMPARATOR INTERRUPT
See Section 7.6 for complete description of comparator
interrupts.
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt ag may not get set.
FIGURE 9-16: INT PIN INTERRUPT TIMING
TABLE 9-8:
SUMMARY OF INTERRUPT REGISTERS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on POR
Reset
Value on all
other resets(1)
0Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
—
CMIF
—
-0-- ----
8Ch
PIE1
—
CMIE
—
-0-- ----
Note1: Other (non power-up) resets include MCLR reset, Brown-out Reset and Watchdog Timer Reset during normal operation.
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
OSC1
CLKOUT
INT pin
INTF ag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
Interrupt Latency
PC
PC+1
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (PC)
Inst (PC+1)
Inst (PC-1)
Inst (0004h)
Dummy Cycle
Inst (PC)
—
1
4
5
1
Note 1: INTF ag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 Tcy. Synchronous latency = 3 Tcy, where Tcy = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
2
3
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