参数资料
型号: PIC16LF818T-I/SS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 10 MHz, RISC MICROCONTROLLER, PDSO20
封装: 0.209 INCH, PLASTIC, MO-150, SSOP-20
文件页数: 148/176页
文件大小: 3124K
代理商: PIC16LF818T-I/SS
2004 Microchip Technology Inc.
DS39598E-page 71
PIC16F818/819
10.0
SYNCHRONOUS SERIAL PORT
(SSP) MODULE
10.1
SSP Module Overview
The Synchronous Serial Port (SSP) module is a serial
interface useful for communicating with other periph-
eral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The SSP module
can operate in one of two modes:
Serial Peripheral Interface (SPI)
Inter-Integrated Circuit (I2C)
An overview of I2C operations and additional informa-
tion on the SSP module can be found in the “PICmicro
Mid-Range
MCU
Family
Reference
Manual”
(DS33023).
Refer to Application Note AN578, “Use of the SSP
Module
in
the
I2C
Multi-Master
Environment”
(DS00578).
10.2
SPI Mode
This
section
contains
register
definitions
and
operational characteristics of the SPI module.
SPI mode allows 8 bits of data to be synchronously
transmitted
and
received
simultaneously.
To
accomplish communication, typically three pins are
used:
Serial Data Out (SDO)
RB2/SDO/CCP1
Serial Data In (SDI)
RB1/SDI/SDA
Serial Clock (SCK)
RB4/SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
Slave Select (SS)
RB5/SS
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>)
and the SSPSTAT register (SSPSTAT<7:6>). These
control bits allow the following to be specified:
Master mode (SCK is the clock output)
Slave mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Clock Edge (output data on rising/falling
edge of SCK)
Clock Rate (Master mode only)
Slave Select mode (Slave mode only)
Note:
Before enabling the module in SPI Slave
mode, the state of the clock line (SCK)
must match the polarity selected for the
Idle state. The clock line can be observed
by reading the SCK pin. The polarity of the
Idle state is determined by the CKP bit
(SSPCON<4>).
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