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参数资料
型号： PIC16LF818T-I/SS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, FLASH, 10 MHz, RISC MICROCONTROLLER, PDSO20
封装： 0.209 INCH, PLASTIC, MO-150, SSOP-20
文件页数： 154/176页
文件大小： 3124K
代理商： PIC16LF818T-I/SS
2004 Microchip Technology Inc.
DS39598E-page 77
PIC16F818/819
10.3.1
SLAVE MODE
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISB<4,1> set). The SSP module will
override the input state with the output data when
required (slave-transmitter).
When an address is matched, or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK) pulse and
then load the SSPBUF register with the received value
currently in the SSPSR register.
Either or both of the following conditions will cause the
SSP module not to give this ACK pulse:
a)
The Buffer Full bit, BF (SSPSTAT<0>), was set
before the transfer was received.
b)
The overflow bit, SSPOV (SSPCON<6>), was
set before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF but bit, SSPIF (PIR1<3>), is set.
Table 10-2 shows what happens when a data transfer
byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condi-
tion. Flag bit BF is cleared by reading the SSPBUF
register while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the SSP
module, are shown in timing parameter #100 and
parameter #101.
10.3.1.1
Addressing
Once the SSP module has been enabled, it waits for a
Start condition to occur. Following the Start condition,
the eight bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
a)
The SSPSR register value is loaded into the
SSPBUF register.
b)
The Buffer Full bit, BF, is set.
c)
An ACK pulse is generated.
d)
SSP Interrupt Flag bit, SSPIF (PIR1<3>), is set
(interrupt is generated if enabled) – on the falling
edge of the ninth SCL pulse.
In 10-bit Address mode, two address bytes need to be
received by the slave device. The five Most Significant
bits (MSbs) of the first address byte specify if this is a
10-bit address. Bit R/W (SSPSTAT<2>) must specify a
write so the slave device will receive the second
address byte. For a 10-bit address, the first byte would
equal ‘1111 0 A9 A8 0’, where A9 and A8 are the
two MSbs of the address.
The sequence of events for 10-bit address is as
follows, with steps 7-9 for slave-transmitter:
1.
Receive first (high) byte of address (bits SSPIF,
BF and bit UA (SSPSTAT<1>) are set).
2.
Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
3.
Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
4.
Receive second (low) byte of address (bits
SSPIF, BF and UA are set).
5.
Update the SSPADD register with the first (high)
byte of address; if match releases SCL line, this
will clear bit UA.
6.
Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
7.
Receive Repeated Start condition.
8.
Receive first (high) byte of address (bits SSPIF
and BF are set).
9.
Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
10.3.1.2
Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
a no Acknowledge (ACK) pulse is given. An overflow
condition is indicated if either bit, BF (SSPSTAT<0>), is
set or bit, SSPOV (SSPCON<6>), is set.
An SSP interrupt is generated for each data transfer
byte. Flag bit, SSPIF (PIR1<3>), must be cleared in
software. The SSPSTAT register is used to determine
the status of the byte.
10.3.1.3
Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RB4/SCK/SCL is held
low. The transmit data must be loaded into the
SSPBUF register which also loads the SSPSR register.
Then pin RB4/SCK/SCL should be enabled by setting
bit, CKP (SSPCON<4>). The master device must
monitor the SCL pin prior to asserting another clock
pulse. The slave devices may be holding off the master
device by stretching the clock. The eight data bits are
shifted out on the falling edge of the SCL input. This
ensures that the SDA signal is valid during the SCL
high time (Figure 10-7).
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PIC16LF819-I/MLTSL 功能描述:8位微控制器 -MCU 3.5 KB FL 256 RAM 16 I/O RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
PIC16LF819-I/P 功能描述:8位微控制器 -MCU 3.5KB 256 RAM 16 I/O RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
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