参数资料
| 型号： | ISL6314IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 25/32页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 1PHASE BUCK 32-QFN |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 6,000 |
| 应用： | 控制器，Intel VR11，AMD CPU |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.38 V ~ 1.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 带卷 (TR) |
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ISL6314
.
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q ? VCC
(EQ. 27)
the MOSFETs. Figures 16 and 17 show the typical upper and
lower gate drives turn-on transition path. The total power
dissipation in the controller itself, P DR , can be roughly
P Qg_Q1 = --- ? Q G1 ? PVCC ? F SW ? N Q1
P BOOT = ---------------------
3
2
P Qg_Q2 = Q G2 ? PVCC ? F SW ? N Q2
estimated as shown in Equation 29:
P DR = P DR_UP + P DR_LOW + P BOOT + ( I Q ? VCC )
P Qg_Q1
3
(EQ. 29)
I DR = ? --- ? Q G1 ? N
P DR_UP = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
? R HI1 + R EXT1 R LO1 + R EXT1 ?
3
? 2
Q1
?
+ Q G2 ? N Q2 ? ? F SW + I Q
(EQ. 28)
? R HI1 R LO1 ? P Qg_Q1
3
In Equations 27 and 28, P Qg_Q1 is the total upper gate drive
P DR_LOW = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
? R HI2 + R EXT2 R LO2 + R EXT2 ?
power loss and P Qg_Q2 is the total lower gate drive power
loss; the gate charge (Q G1 and Q G2 ) is defined at the
particular gate to source drive voltage PVCC in the
? R HI2 R LO2 ? P Qg_Q2
2
R EXT1 = R G1 + -------------
N
R EXT2 = R G2 + -------------
N
corresponding MOSFET data sheet; I Q is the driver total
quiescent current with no load at both drive outputs; N Q1 and
N Q2 are the number of upper and lower MOSFETs
R GI1
Q1
R GI2
Q2
respectively. The I Q* VCC product is the quiescent power of
the controller without capacitive load and is typically 75mW at
300kHz.
Inductor DCR Current Sensing Component
Selection
For accurate load line regulation, the ISL6314 senses the
PVCC
BOOT
C GD
D
total output current by detecting the voltage across the
output inductor DCR (as described in “Load-Line (Droop)
network is required to accurately sense the inductor DCR
I OUT
L
R HI1
R LO1
PHASE
UGATE
G
R G1
R GI1
C GS
S
C DS
Q1
voltage and convert this information into a “droop” voltage,
which is proportional to the total output current.
V L (s)
L
DCR
PHASE
INDUCTOR V OUT
I
FIGURE 16. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
D
ISEN-
R S
C OUT
C GD
ISENO
C COMP
R COMP
R HI2
R LO2
LGATE
G
R G2
R GI2
C DS
-
V DROOP
ISEN+
+
(OPTIONAL)
C GS
S
Q2
ISL6314
FIGURE 18. DCR SENSING CONFIGURATION
FIGURE 17. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
path resistance, P DR_UP , the lower drive path resistance,
P DR_UP , and in the boot strap diode, P BOOT . The rest of the
power will be dissipated by the external gate resistors (R G1
and R G2 ) and the internal gate resistors (R GI1 and R GI2 ) of
25
Choosing the components for this current sense network is a
two step process. First, R COMP and C COMP must be
chosen so that the time constant of this R COMP - C COMP
network matches the time constant of the inductor L/DCR.
Then the resistor R S must be chosen to set the current
sense network gain, obtaining the desired full load droop
voltage. Follow the steps outlined in the following to choose
the component values for this R-C network.
FN6455.2
October 8, 2009
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