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参数资料
型号： PM4314-RI
厂商： PMC-SIERRA INC
元件分类： 数字传输电路
英文描述： QUAD T1/E1 LINE INTERFACE DEVICE
中文描述： DATACOM, PCM TRANSCEIVER, PQFP128
封装： PLASTIC, QFP-128
文件页数： 109/170页
文件大小： 823K
代理商： PM4314-RI
PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
97
OOSI:
The OOSI bit shows the current status of the interrupt signal. A logic 1 in this
bit position indicates that a change in PRBS synchronization state has
occurred. A logic 0 indicates that no change in PRBS synchronization state
has occurred. The OOSI bit is cleared following a read of this register.
OOS:
The OOS bit indicates the current PRBS synchronization status of the PRSM
block. A logic 1 in this bit position indicates that the PRSM block is out of
sync. When out of sync, bit error events are not accumulated. A logic 0
indicates that the PRSM block is synchronized and accumulating bit error
events.
INTE:
The INTE bit controls the generation of a microprocessor interrupt when the
transfer clock has caused the counter values to be stored in the holding
registers. A logic 1 bit in the INTE position enables the generation of an
interrupt; a logic 0 bit in the INTE position disables the generation of an
interrupt. The interrupt is cleared (acknowledged) by reading this register.
INT:
The INT bit is the current status of the interrupt signal. A logic 1 in this bit
position indicates that a transfer has occurred. A logic 0 indicates that no
transfer has occurred. The INT bit is cleared following a read of this register.
OVR:
The OVR bit holds the overrun status of the holding registers. A logic 1 in this
bit position indicates that a previous interrupt has not been acknowledged
before the next transfer clock has been issued and that the contents of the
holding registers have been overwritten. A logic 0 indicates that no overrun
has occurred. The OVR bit is cleared by reading this register.
Latching Performance Data
The Pseudo-Random Sequence Monitor (PRSM) holding registers (02AH-02BH,
06AH-06BH, 0AAH-0ABH, and 0EAH-0EBH) are updated by a microprocessor
write to either of the particular PRSM's holding registers. The PRSM block is
loaded with new performance data within 4 clock periods (RCLKO[X] if in the
receive path, TCLKI[X] if in the transmit path) after the write. Thus, the PRSM
holding registers should not be read until after 2 μs (E1 case) or 2.6 μs (DSX-1
case) has elapsed since the write was completed. Alternatively, the PRSM
Control/Status register may be polled until the INT bit goes to logic 1, indicating
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