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参数资料
型号： PM4314-RI
厂商： PMC-SIERRA INC
元件分类： 数字传输电路
英文描述： QUAD T1/E1 LINE INTERFACE DEVICE
中文描述： DATACOM, PCM TRANSCEIVER, PQFP128
封装： PLASTIC, QFP-128
文件页数： 133/170页
文件大小： 823K
代理商： PM4314-RI
PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
121
applications). Consequently, the frequency of the clock inputs to the phase
discriminator in the PLL is 8 kHz. The DJAT SYNC option must be disabled since
the divisor magnitude of 193 or 256 is not an integer multiple of the FIFO length
48.
The DJAT phase lock loop has a single order low pass jitter transfer function. By
default, the corner frequency is 8.8 Hz. The corner may be moved by the
appropriate selection of clock divisors:
f
c
=
(
)
1
+
2
N
1536
f
t
π
where
f
c
=
corner frequency
ft
=
TCLKI[X] average
frequency
value in the Output
Clock Divisor
Control register
N2=
Ensure the Reference Clock Divisor Control value (N1) is also modified to be
equal to the Output Clock Divisor Control value(N2).
The self-centering circuitry of the FIFO should be enabled by setting the CENT
register bit. This sets up the FIFO read pointer to be at least 4 UI away from the
end of the FIFO registers, and then disengages. Should variations in the
frequency of input clock or the output clock cause the read pointer to drift to
within one unit interval of FIFO overflow or underflow, the pointer will be
incrementally pushed away by the LIMIT control without any loss of data.
With SYNC disabled, and CENT and LIMIT enabled, the maximum tolerable
phase difference between the bursty input clock and the smooth "jitter-free" clock
is 40UI. Phase wander between the two clock signals is compensated for by the
LIMIT control.
12.3 Using XPLS without DJAT
The XPLS requires an 8X clock that is synchronous to its transmit clock, and
which satisfies particular setup and hold requirements with respect to that
transmit clock. When the DJAT PLL is in the transmit stream, it provides the
necessary clocks. Should the DJAT be bypassed or in the receive stream, or
should a 24X clock not be available to the PLL, alternate arrangements must be
made to supply XPLS with its required clocks. The possible cases are: a)
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PM43-150M-RC 功能描述:固定电感器 15uH 20% RoHS:否 制造商:AVX 电感:10 uH 容差:20 % 最大直流电流:1 A 最大直流电阻:0.075 Ohms 工作温度范围:- 40 C to + 85 C 自谐振频率:38 MHz Q 最小值:40 尺寸:4.45 mm W x 6.6 mm L x 2.92 mm H 屏蔽:Shielded 端接类型:SMD/SMT 封装 / 箱体:6.6 mm x 4.45 mm
PM4318 制造商:PMC 制造商全称:PMC 功能描述:OCTAL E1/T1/J1 LINE INTERFACE DEVICE
PM43-180M 功能描述:固定电感器 18 UH 4X4.5X3.2 MM RoHS:否 制造商:AVX 电感:10 uH 容差:20 % 最大直流电流:1 A 最大直流电阻:0.075 Ohms 工作温度范围:- 40 C to + 85 C 自谐振频率:38 MHz Q 最小值:40 尺寸:4.45 mm W x 6.6 mm L x 2.92 mm H 屏蔽:Shielded 端接类型:SMD/SMT 封装 / 箱体:6.6 mm x 4.45 mm
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