STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
169
BEEE:
The BEEE bit enables the generation of an interrupt when a bit error event
has been detected. A bit error event is defined as framing bit errors for SF
formatted data, CRC-6 mismatch errors for ESF formatted data, Ft bit errors
for SLC96 formatted data, and either framing bit errors or sync word errors
for T1DM formatted data. When BEEE is set to logic 1, the detection of a bit
error event is allowed to generate an interrupt. When BEEE is set to logic 0,
bit error events are disabled from generating an interrupt on the INTB pin.
SFEE:
The SFEE bit enables the generation of an interrupt when a severely errored
framing event has been detected. A severely errored framing event is defined
as 2 or more framing bit errors during the current superframe for SF, ESF, or
SLC96 formatted data, and 2 or more framing bit errors or sync word errors
during the current superframe for T1DM formatted data. When SFEE is set
to logic 1, the detection of a severely errored framing event is allowed to
generate an interrupt. When SFEE is set to logic 0, severely errored framing
events are disabled from generating an interrupt on the INTB pin.
MFPE:
The MFPE bit enables the generation of an interrupt when the frame find
circuitry detects the presence of framing bit mimics. The occurrence of a
mimic is defined as more than one framing bit candidate following the frame
alignment pattern. When MFPE is set to logic 1, the assertion or deassertion
of the detection of a mimic is allowed to generate an interrupt. When MFPE is
set to logic 0, the detection of a mimic framing pattern is disabled from
generating an interrupt on the INTB pin.
INFRE:
The INFRE bit enables the generation of an interrupt when the frame find
circuitry determines that frame alignment has been achieved and that the
framer is now "inframe". When INFRE is set to logic 1, the assertion or
deassertion of the "inframe" state is allowed to generate an interrupt. When
INFRE is set to logic 0, a change in the "inframe" state is disabled from
generating an interrupt on the INTB pin.
Upon reset of the COMET, these bits are set to logic 0, disabling the generation
of interrupts on the INTB pin.