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STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
252
E1-TRAN International Bits Control register and the E1-TRAN National bits
are ignored and the values for those bit positions in the output stream are
taken directly from the BTPCM stream. When INDIS and FDIS are logic 0,
the bit values used for the International and National bits are dependent upon
the values of the GENCRC and FEBEDIS configuration bits, as shown in the
following table:
Table 60
- E1 Timeslot 0 Bit 1 Insertion Control Summary
GENCRC
FEBEDIS
Source of International Bits
0
X
Bit position Si[1] in the International Bits Control
register is used for the International bit in the frame
alignment signal (FAS) frames and the Si[0] bit in the
non-frame alignment signal (NFAS) frames if INDIS is
logic 0. BTPCM replaces Si[1:0] if INDIS is logic 1.
The calculated CRC bits are used for the International
bit in the FAS frames and the generated CRC
multiframe alignment signal and the FEBE bits are
used for the International bit in the NFAS frames.
The calculated CRC bits are used for the International
bit in the FAS frames and the generated CRC
multiframe alignment signal is used for the International
bit in the NFAS frames, with the Si[1:0] bits in the
International Bits Control register used for the spare
bits.
1
0
1
1
XDIS:
If FDIS is logic 0 and SIGEN is logic 1, the XDIS bit controls the insertion of
the Extra bits in TS16 of
frame 0 of the signaling
multiframe as follows.
When XDIS is set to a logic 0, the contents of
the E1-TRAN Extra Bits
Control
Register are inserted into TS16, frame 0; when XDIS is a logic 1, the contents
of the register are ignored and the values for those bits positions in the output
stream are taken directly from the BTPCM stream. That is, when XDIS and
FDIS are logic 0 and SIGEN is logic 1, the X1, X3 and X4 bit values from the
E1-TRAN Extra Bits Control Register are used for the Extra bits in TS16 of
frame 0 of the signaling multiframe.
When the COMET is reset, the contents of this register are set to logic 0, except
SIGEN and DLEN which are set to logic 1.