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STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
364
BRFP is expected to be aligned to the first bit of the frame. Once the RATE[1:0]
bits are set, a reset is required to change to a new RATE[1:0].
Figure 31
- Receive Backplane at 4.096 Mbit/s (T1 Mode)
TS 31
BRFP
4.096 MHz BRCLK
(CMS = 0)
BRPCM
TS 30
TS 0
TS 1
F
X
BRSIG
A
D
B
C
A
D
B
C
A
D
B
C
X
X
X
A 4.096 Mbit/s backplane in T1 mode is configured by setting the RATE[1:0] bits
of the Receive Backplane Configuration register to 'b10 and the E1/T1B bit of the
Global Configuration register to logic 0. In Figure 31, BRFP, BRPCM and BRSIG
are configured to be updated on the falling edge of BRCLK by setting the FE and
DE bits of the Receive Backplane Configuration register to logic 0. TSOFF[6:0]
is set to 'b0000000 so that the first of the two interleaved bytes is sampled. Once
the RATE[1:0] bits are set, a reset is required to change to a new RATE[1:0].
In Figure 31, the MAP register bit is logic 0. As shown, every fourth time slot is
unused, starting with the first. If MAP is a logic 1, time slots 0 through 23 would
be used. The framing bit is presented during bit 0 of time slot 0, so that only bits
1 to 7 of time slot 0 are ignored. The TSOFF[6:0], BOFF_EN and BOFF[2:0]
register bits are all logic zero; therefore, BRFP is expected to be aligned to the
first bit of the frame.
Figure 32
- Receive Backplane at 4.096 Mbit/s (E1 Mode)
TS 31
BRFP
4.096 MHz BRCLK
(CMS = 0)
BRPCM
BRSIG
A
D
B
C
A
D
B
C
A
D
B
C
X
X
X
TS 30
TS 0
TS 1
A 4.096 Mbit/s backplane in E1 mode is configured by setting the RATE[1:0] bits
of the Receive Backplane Configuration register to 'b10 and the E1/T1B bit of the
Global Configuration register to logic 1. In Figure 32, BRFP, BRPCM and BRSIG
are configured to be updated on the falling edge of BRCLK by setting the FE and
DE bits of the Receive Backplane Configuration register to logic 0. TSOFF[6:0]
is set to 'b0000000 so that the first of the two interleaved bytes is sampled. Once
the RATE[1:0] bits are set, a reset is required to change to a new RATE[1:0].