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参数资料
| 型号： | PM4541 |
| 厂商： | PMC-Sierra, Inc. |
| 英文描述： | T1XC EVALUATION DAUGHTER BOARD |
| 中文描述： | T1XC评价子板 |
| 文件页数： | 10/46页 |
| 文件大小： | 520K |
| 代理商： | PM4541 |
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TELECOM STANDARD PRODUCT
PMC-Sierra, Inc.
PM4541 T1XC-EVBD
PMC-920314
ISSUE 2
T1XC EVALUATION DAUGHTERBOARD
7
AD[1]
I/O
C19
Multiplexed address/data bus bit 1
AD[0]
I/O
C20
Multiplexed address/data bus bit 0
PA3
O
C21
68HC11 Processor Port A bit 3
PA4
O
C22
68HC11 Processor Port A bit 4
PA5
O
C23
68HC11 Processor Port A bit 5
PA6
O
C24
68HC11 Processor Port A bit 6
PD2
I
C25
MISO. Master In Slave Out of Port D acting as SPI.
Pulled up on motherboard.
PD3
O
C26
MOSI. Master Out Slave In of Port D acting as SPI.
Pulled up on motherboard.
PD4
O
C27
SCK. Serial clock of Port D acting as SPI. Pulled up
on motherboard.
PD5
O
C28
SS. Slave Select of Port D acting as SPI active low.
Pulled up on motherboard.
IRQ
I
C29
Maskable interrupt
XIRQ
I
C30
Non Maskable Interrupt
DISB
I
C31
EVMB memory disable. Pulling this signal low will
disable MPU access to the EVMB's on-board RAM
and EPROM.
SP
O
C32
SPARE
GND
O
A1-
A28
Ground
+5V
O
A29-
A32
+5 Volts
3.2 Header Connections
All T1XC functional pins are connected to male header strips to provide as much
access as possible. These headers may be used as probe points or as a means to
build sample applications by making appropriate connections between points. Each
T1XC can run in isolation of the other, thus any application, other than the default
sample "CSU", will require header connections to be made.
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