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参数资料
| 型号： | PM4541 |
| 厂商： | PMC-Sierra, Inc. |
| 英文描述： | T1XC EVALUATION DAUGHTER BOARD |
| 中文描述： | T1XC评价子板 |
| 文件页数： | 11/46页 |
| 文件大小： | 520K |
| 代理商： | PM4541 |
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TELECOM STANDARD PRODUCT
PMC-Sierra, Inc.
PM4541 T1XC-EVBD
PMC-920314
ISSUE 2
T1XC EVALUATION DAUGHTERBOARD
8
3.2.1 External Signal Header
This header is provided to accept an external clock and framing pulse source. These
inputs are then buffered for use on the board. External clock sources must be
buffered through this header to avoid possible damage to the T1XCs or DPLL.
Signal
Type
Ref.
Description
EXTFP
I
J26-2
External Framing Pulse Input
EXTCLK
I
J26-4
External Clock Input
BEXTFP
O
J27-1
Buffered External Framing Pulse
BEXTCLK
O
J27-2
Buffered External Clock
3.2.2 DPLL Header
This header is provided to give access to the clock generating MT8940 DPLL chip
as well as provide direct oscillator access. All of the major DPLL outputs are brought
out to this header even though they may be of limited use with the T1XC (e.g. the
4.096 MHz clock).
Signal
Type
Ref.
Description
FPIN
I
J29-2
1.544 MHz Framing pulse input to MT8940.
C8KB
I/O
J29-1
2.048 MHz Framing pulse in/out (mode dependent).
GFP
I/O
J29-3
8 kHz Framing pulse output from the MT8940. Note
that this active low output signal is derived from the
16.388 MHz clock and has a 244ns pulsewidth. This
frame pulse signal signal should only be routed to
the T1XC when the backplane is configured for
2.048 MHz; this signal is not suitable when the
T1XC backplane is 1.544 MHz.
C1M5
O
J29-4
1.544 MHz Output clock from MT8940.
C1M5B
O
J29-5
Inverted C1M5 clock.
C2M
O
J29-6
2.048 MHz output clock from MT8940.
C2MB
O
J29-7
Inverted C2M clock.
C4M
O
J29-8
4.096 MHz Output clock from MT8940.
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