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参数资料
| 型号： | PM4541 |
| 厂商： | PMC-Sierra, Inc. |
| 英文描述： | T1XC EVALUATION DAUGHTER BOARD |
| 中文描述： | T1XC评价子板 |
| 文件页数： | 23/46页 |
| 文件大小： | 520K |
| 代理商： | PM4541 |
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TELECOM STANDARD PRODUCT
PMC-Sierra, Inc.
PM4541 T1XC-EVBD
PMC-920314
ISSUE 2
T1XC EVALUATION DAUGHTERBOARD
20
4
0100
Divide-1 Mode:
Divides the CVB input
signal by 193. The divided
output is connected to
DPLL #2
Divide-1 Mode
Externally applied 4.096
MHz. clock and 8 kHz.
frame pulse, properly phase
related, are used to
generate the 2.048 MHz
output clock.
Single Clock-1 Mode:
5
0101
Operates as above
Provides the CEPT/ST-BUS
compatible timing signals
locked to an 8 kHz. internal
signal provided by DPLL
#1.
Same as 'mode 2'
Single Clock-1 Mode
Same as 'mode 0'
F0B becomes an input.
DPLL #2 provides the ST-
BUS signals locked onto
F0B input only if it is 16
kHz.
Same as 'mode 2'
Free Run Mode
6
7
8
9
0110
0111
1000
1001
Divide-1 Mode
Divide-1 Mode
Normal Mode
Normal Mode
10
11
1010
1011
Normal Mode
Normal Mode
Provides the CEPT/ST-BUS
compatible timing and
framing signals with no
external inputs other than
the master clock.
Same as 'mode 0'
12
1100
Divide-2 Mode:
Divides the CVB input by
256. The divided output is
connected to DPLL #2
Divide-2 Mode
13
1101
Single Clock-2 Mode:
Provides the CEPT/ST-BUS
signals locked to the 8 kHz.
internal signal provided by
DPLL #1
Same as 'mode 2'
Single Clock-2 Mode
14
15
1110
1111
Divide-2 Mode
Divide-2 Mode
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