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| 型号： | PM4541 |
| 厂商： | PMC-Sierra, Inc. |
| 英文描述： | T1XC EVALUATION DAUGHTER BOARD |
| 中文描述： | T1XC评价子板 |
| 文件页数： | 24/46页 |
| 文件大小： | 520K |
| 代理商： | PM4541 |
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TELECOM STANDARD PRODUCT
PMC-Sierra, Inc.
PM4541 T1XC-EVBD
PMC-920314
ISSUE 2
T1XC EVALUATION DAUGHTERBOARD
21
6.4 T1XC
Two T1XCs can be socketed into the daughterboard. Each is individually accessible
and can run independently of the other. All pins except for the microprocessor
interface and power pins are connected to header strips for easy test equipment
access. Analog receive power pin RAVD is connected to a jumper to enable tying to
either ground or power. Tying this pin to ground will disable the internal RSLC TSB,
reducing the power consumed. Tying the RAVD pin to VCC enables the normal
operating mode. All other power pins are appropriately decoupled and all inputs are
tied high through 10 k
resistors SIPs.
For a more detailed description of the T1XC and its features, refer to the T1XC
Standard Product datasheet.
6.5 "CSU" DIPs and Jumpers
Normally, the two T1XCs run independently of each other except when explicit
connections are made between the two devices. To facilitate testing of a simple
application involving two devices appropriate control signals have been wired to two
16 pin DIP sockets and six jumpers to enable hooking up the T1XCs in a "CSU"-like
application.
Both T1XCs are connected in a symmetrical fashion and most connections are
completed by installing shorting bar jumpers into the two 16 pin DIP sockets labeled
for the CSU set-up. The remaining unconnected signals are BRCLK, BRFPI, and
BTCLK. By installing jumpers across pins 1 and 2 of each of jumper blocks J19 and
J20, between pins 3 and 4 of each of the jumper blocks J21, J22, J23, J24, and
between pin 2 and 3 of jumper block J30, a "CSU" like application can be
implemented where the 1.544 MHz clock for the backplane between the two T1XC
devices is provided by the MT8940, which in turn is locked to the recovered clock
provided by T1XC #1. Bits 1 and 2 of SW1 must be closed; the remaining bits open.
By appropriately making jumper connections to the other available clock options, the
backplane can be run at different rates, such as 1.544 MHz, 2.048 MHz, or at an
externally supplied clock rate.
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