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参数资料
| 型号： | PM6670STR |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 稳压器 |
| 英文描述： | 3 A SWITCHING CONTROLLER, QCC24 |
| 封装： | 4 X 4 MM, LEAD FREE, VFQFPN-24 |
| 文件页数： | 51/54页 |
| 文件大小： | 742K |
| 代理商： | PM6670STR |
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Pin settings
PM6670S
6/54
Doc ID 14432 Rev 4
2.2
Pin description
Table 2.
Pin functions
N°
Pin
Function
1
VTTGND
LDO power ground. Connect to negative terminal of VTT output capacitor.
2VTTSNS
LDO remote sensing. Connect as close as possible to the load via a low
noise PCB trace.
3DDRSEL
DDR voltage selector (if MODE is tied to VCC) or pulse-skip/no-audible
pulse-skip selector in adjustable mode (MODE voltage lower than 3 V). See
4VTTREF
Low noise buffered DDR reference voltage. A 22 nF (minimum) ceramic
bypass capacitor is required in order to achieve stability.
5SGND
Ground reference for analog circuitry, control logic and VTTREF buffer.
Connect together with the thermal pad and VTTGND to a low impedance
ground plane. See the Application Note for details.
6AVCC
+5 V supply for internal logic. Connect to +5 V rail through a simple RC
filtering network.
7VREF
High accuracy output voltage reference (1.237 V) for multilevel pins setting.
It can deliver up to 50
μA. Connect a 100 nF capacitor between VREF and
SGND in order to enhance noise rejection.
8VOSC
Frequency selection. Connect to the central tap of a resistor divider to set
the desired switching frequency. The pin cannot be left floating. See
9
VSNS
VDDQ output remote sensing. Discharge path for VDDQ in Non-Tracking
Discharge. Input for internal resistor divider that provides VDDQ/2 to
VTTREF and VTT. Connect as close as possible to the load via a low noise
PCB trace.
10
MODE
Mode of operation selector. If MODE pin voltage is higher than 4 V, the fixed
output mode is selected. If MODE pin voltage is lower than 4 V, it is used as
negative input of the error amplifier. See Section 7.1.4: Mode-of-operation
11
COMP
DC voltage error compensation Input for the switching section. Refer
12
DSCG
Discharge mode selection. Refer to Section 7.1.8: VDDQ output discharge
on page 34 for tracking/non-tracking discharge or no-discharge options.
13
S5
Switching controller enable. Connect to S5 system status signal to meet S0-
S5 power management states compliance. See Section 7.3: S3 and S5
power management pins on page 38, S5 pin can't be left floating.
14
S3
Linear regulator enable. Connect to S3 system status signal to meet S0-S5
power management states compliance. See Section 7.3: S3 and S5 power
management pins on page 38, S3 pin can't be left floating.
15
PG
Power Good signal (open drain output). High when VDDQ output voltage is
within ±10 % of nominal value.
16
PGND
Power ground for the switching section.
17
LGATE
Low-side gate driver output.
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