
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
PM7340 S/UNI-IMA-8
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
97
11
NORMAL MODE REGISTER DESCRIPTION
Normal mode registers are used to configure and monitor the operation of the
S/UNI-IMA-8. Normal mode registers (as opposed to test mode registers) are
selected when A[10] is low.
Notes on Normal Mode Register Bits:
1. Writing values into unused register bits has no effect. However, to ensure software
compatibility with future, feature-enhanced versions of the product, unused register
bits must be written with logic zero. Reading back unused bits can produce either a
logic one or a logic zero; hence, unused register bits should be masked off by
software when read.
2. All configuration bits that can be written into can also be read back. This allows the
processor controlling the S/UNI-IMA-8 to determine the programming state of the
block.
3. Writeable normal mode register bits are cleared to logic zero upon reset unless
otherwise noted.
4. Writing into read-only normal mode register bit locations does not affect S/UNI-IMA-8
operation unless otherwise noted.
5. Certain register bits are reserved. These bits are associated with megacell functions
that are unused in this application. To ensure that the S/UNI-IMA-8 operates as
intended, reserved-register bits must only be written with logic zero. Similarly, writing
to reserved registers should be avoided.