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参数资料
型号： PM7351-BI
厂商： PMC-SIERRA INC
元件分类： 数字传输电路
英文描述： OCTAL SERIAL LINK MULTIPLEXER
中文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PBGA304
封装： 31 X 31 MM, 1.51 MM HEIGHT, 1.27 MM PITCH, SBGA-304
文件页数： 152/174页
文件大小： 1790K
代理商： PM7351-BI
RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
142
If the cell is not the first of the message, write the Insert CRC-32 Accumulator
register with the value stored at the end of the previous cell for the same
control channel. This step is not necessary if the last cell inserted belonged
to the same control channel as the current cell.
Insertion of the CRC-32 field is done by setting the INSCRCEND bit of the
Microprocessor Insert FIFO Control register to logic 1 prior to writing the last
cell of the CPCS-PDU. The S/UNI-VORTEX will overwrite the data of the last
four bytes of the cell payload written by the microprocessor with the ones
complement of the content of the Insert CRC-32 Accumulator register.
3. Select the Insert FIFO by writing its identification number to the INSFSEL[2:0]
field of the Insert FIFO Control register.
4. Write the cell contents to the Microprocessor Cell Data register. Cell data is
entered in the format illustrated in Fig. 7.
5. If the cell is not the last of the message, read and store the contents of the
Insert CRC-32 accumulator register. This step is not necessary if the next cell
to be inserted belongs to the same control channel as the current cell.
The above sequence is repeated as needed to insert more cells. The assertion
of a INSRDY bit of the Insert FIFO indicates that the associated FIFO is ready
again to be written to. Setting INSRST of the Insert FIFO Control register to logic
1 prior to writing the last cell byte allows the overwriting of the cell data.
12.5.2 Reading Cell Data From a Control Channel
Reading cell data from a control channel is done by manipulating the
Microprocessor Extract FIFO Control and Microprocessor Extract FIFO Ready
registers. The following steps are required to read a cell from one of the Extract
FIFOs.
1. Poll the EXTRDY[7:0] bits in the Microprocessor Extract FIFO Ready register.
The EXTRDY[n] bit indicates the status of the FIFO receiving control channel
cells from the RXDn+/- high speed link. Alternately, service the interrupts that
result from setting the EXTRDYE bit in the Microprocessor Cell Buffer
Interrupt Control and Status register.
2. Select the Extract FIFO corresponding to the desired high speed link by
writing its identification number to the EXTFSEL bit of the Microprocessor
Extract FIFO Control register.
3. Read the header of the cell to determine if it is the end of message and to
which virtual channel it belongs.
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