
STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PROPRIETARY AND CONFIDENTIAL
306
Table 65
- Transmit Line Interface Timing (Figure 110)
Symbol
Description
Min
Max
Units
CTCLK Frequency (when used for TJAT
REF), typically 1.544 MHz± 130 ppm for
T1 operation or 2.048 MHz± 50 ppm for E1
operation
2,3,6
1.5
2.1
MHz
tHCTCLK
CTCLK High Duration
4
(when used for
TJAT REF)
100
ns
tLCTCLK
CTCLK Low Duration
4
(when used for
TJAT REF)
100
ns
Figure 110
- Transmit Line Interface Timing
CTCLK
t
L
t
H
t
CTCLK
CTCLK
CTCLK
Notes on Ingress and Egress Serial Interface Timing:
1. CECLK and CICLK can be gapped and/or jittered clock signals subject to the
minimum high and low times shown. These specifications correspond to
nominal XCLK input frequencies.
2. Guaranteed by design for nominal XCLK input frequency (37.056 MHz ±100
ppm for T1 modes and 49.152 MHz ±50ppm for E1 modes).
3. CTCLK can be a jittered clock signal subject to the minimum high and low
times shown. These specifications correspond to nominal XCLK input
frequency of 37.056 MHz ±100 ppm for T1 modes and 49.152 MHz ±50ppm
for E1 modes.
4. High pulse width is measured from the 1.4 Volt points of the rise and fall
ramps. Low pulse width is measured from the 1.4 Volt points of the fall and
rise ramps.