
STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PROPRIETARY AND CONFIDENTIAL
42
Pin Name
Type
Pin
No.
Function
CICLK
Input
N1
Common Ingress Clock (CICLK).
CICLK is either a
1.544MHz clock in T1 mode or a 2.048MHz clock in T1
or E1 modes, with optional gapping for adaptation to
non-uniform backplane data streams. CICLK is
common to all 28 T1 or 21 E1 framers. CIFP is
sampled on the active edge of CICLK.
When the Clock Slave ingress modes are active, ID[x],
ISIG[x], and IFP[x] are updated on the active edge of
CICLK.
CICLK is a nominal 1.544 or 2.048 MHz clock +/-
50ppm with a 50% duty cycle.
This signal shares a pin with the H-MVIP signal
CMVFPC. By default this input is CICLK.
CIFP
Input
P4
Common Ingress Frame Pulse (CIFP).
When the
elastic store is enabled (Clock Slave mode is active on
the ingress side), CIFP is used to frame align the
ingress data to the system frame alignment. CIFP is
common to all 28 T1 or 21 E1 framers. When frame
alignment is required, a pulse at least 1 CICLK cycle
wide must be provided on CIFP a maximum of once
every frame (nominally 193 or 256 bit times).
CIFP is sampled on the active edge of CICLK as
selected by the CIFE bit in the Master Common
Ingress Serial and H-MVIP Interface Configuration
register.