SBSLITE Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
108
Register 031H: ICASM CAS Enable Indirect Access Control Register
Bit
Type
Function
Default
Bit 15-8
R
Unused
0
Bit 7
R
BUSY
0
Bit 6
R
HST_ADDR_ERR
0
Bit 5
R
Unused
0
Bit 4
R
Unused
0
Bit 3
R
Unused
0
Bit 2
R
Unused
0
Bit 1
R/W
RWB
0
Bit 0
R
Unused
0
RWB
The indirect access control bit (RWB) selects between a configure (write) or interrogate
(read) access to the CAS Enable register. Writing a ‘0’ to RWB triggers an indirect write
operation. Data to be written is taken from the CAS Enable Indirect Access Data register.
Writing a ‘1’ to RWB triggers an indirect read operation. The data read can be found in the
CAS Enable Indirect Access Data register.
HST_ADDR_ERR
When set following a host read this bit indicates that an illegal host access was attempted. An
illegal host access occurs when an attempt is made to access an out of range tributary. Out of
range tributaries accesses occur when SBI[2:0] is not in the range 1-4, SPE[1:0] is not in the
range 1-3 and TRIB[4:0] is not in the range 1-28 for T1s, not in the range 1-21 for E1s and
not equal to 1 for the remaining tributary types. This bit is cleared when this register is read.
BUSY
The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set
high when a write to the CAS Enable Indirect Access Control register triggers an indirect
access and will stay high until the access is complete. This register should be polled to
determine when data from an indirect read operation is available in the CAS Enable Indirect
Access Data register or to determine when a new indirect write operation may commence.