SBSLITE Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
92
Register 015H: SBSLITE Master Signal Monitor #2
Bit
Type
Function
Default
Bit 15
R
Reserved
X
Bit 14
R
Reserved
X
Bit 13
R
Reserved
X
Bit 12
R
ITPLA
X
Bit 11
R
Reserved
X
Bit 10
R
Reserved
X
Bit 9
R
Reserved
X
Bit 8
R
IV5A
X
Bit 7
R
Reserved
X
Bit 6
R
Reserved
X
Bit 5
R
Reserved
X
Bit 4
R
IPLA
X
Bit 3
R
Reserved
X
Bit 2
R
Reserved
X
Bit 1
R
Reserved
X
Bit 0
R
IDATAA
X
This register provides activity monitoring on major SBSLITE inputs. When a monitored input
makes a low to high transition, the corresponding register bit is set high. The bit will remain high
until this register is read, at which point, all the bits in this register are cleared. Bits that depend
on multiple inputs making a low to high transition must have each input make a low to high
transition between subsequent reads before the activity bit will be set high. The corresponding
register bit reading low indicates a lack of transitions. This register should be read periodically to
detect for stuck at conditions.
ITPLA
The ITPL active bit (ITPLA) detects low to high transitions on the ITPL input. ITPLA is set
high when a rising edge has been observed on the ITPL input, and is set low when this
register is read.
IV5A
The IV5 active bit (IV5A) detects low to high transitions on the IV5 input. IV5A is set high
when a rising edge has been observed on the IV5 input, and is set low when this register is
read.
IPLA
The IPL active bit (IPLA) detects low to high transitions on the IPL input. IPLA is set high
when a rising edge has been observed on the IPL input, and is set low when this register is
read.