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参数资料
| 型号： | PowerNP NPe405L |
| 厂商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Processor(32位嵌入式处理器) |
| 中文描述： | 32位嵌入式处理器（32位嵌入式处理器） |
| 文件页数： | 11/48页 |
| 文件大小： | 741K |
| 代理商： | POWERNP NPE405L |
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Advance Information
PowerNP
TM
NPe405L Embedded Processor Data Sheet
11
General Purpose IO (GPIO) Controller
Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus
master accesses
Most GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO
capabilities acts as a GPIO or is used for another purpose. The GPIO function has 32 I/Os.
Each GPIO output is separately programmable to emulate an open-drain driver (drives to zero, three-
stated if output bit is 1)
Universal Interrupt Controller (UIC)
Two cascaded Universal Interrupt Controllers (UICs) provides the control, status, and communications
necessary between the various sources of interrupts and the local PowerPC processor.
Features include:
Supports 7 external and 29 internal interrupts
Edge triggered or level-sensitive
Positive or negative active
Non-critical or critical interrupt to PPC405 processor core
Programmable critical interrupt priority ordering
Programmable critical interrupt vector for faster vector processing
10/100 Mbps Ethernet MAC
Two units capable of full- or half-duplex operation at up to 100Mbps
ZMII Bridge to external Ethernet PHYs that support
- Reduced Media Independent Interface (RMII) or Serial Media Independent Interface (SMII) for
multiple PHY applications
- Media Independent Interface (MII) for single PHY applications
Dedicated DMA channel
JTAG
IEEE 1149.1 Test Access Port
IBM RISCWatch Debugger support
JTAG Boundary Scan Description Language (BSDL)
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