参数资料
型号: PowerNP NPe405L
厂商: IBM Microeletronics
英文描述: 32-Bit Embedded Processor(32位嵌入式处理器)
中文描述: 32位嵌入式处理器(32位嵌入式处理器)
文件页数: 47/48页
文件大小: 741K
代理商: POWERNP NPE405L
Advance Information
PowerNP
TM
NPe405L Embedded Processor Data Sheet
47
Initialization
The following describes the method by which initial chip settings are established when a system reset occurs.
Pin Strapping
While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable default initial
conditions prior to NPe405L start-up. The actual capture instant is the nearest reference clock edge before
the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down
(logical 0) resistors to select the desired default conditions. These pins are use for strap functions only during
reset. They are used for other signals during normal operation. The following table lists the strapping pins
along with their functions and strapping options.
Strapping Pin Assignments
Function
Option
Ball Strapping
Width of boot device on EBC data bus
Y21
8 bits
0
16 bits
1
Ethernet ZMII mode
V21
U20
MII mode
0
0
SMII mode
0
1
RMII 10 Mbps mode
1
0
RMII 100 Mbps mode
1
1
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