- 您现在的位置：买卖IC网 > PDF目录370013 > PowerNP NPe405L (IBM Microeletronics) 32-Bit Embedded Processor(32位嵌入式处理器) PDF资料下载
参数资料
| 型号： | PowerNP NPe405L |
| 厂商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Processor(32位嵌入式处理器) |
| 中文描述： | 32位嵌入式处理器（32位嵌入式处理器） |
| 文件页数： | 28/48页 |
| 文件大小： | 741K |
| 代理商： | POWERNP NPE405L |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页当前第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页
Advance Information
PowerNP
TM
NPe405L Embedded Processor Data Sheet
28
Signal Functional Description
(Part 1 of 6)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
to 3.3V, 10k
to 5V
)
3. Must pull down (recommended value is 1k
)
4. If not used, must pull up (recommended value is 3k
to 3.3V)
5. If not used, must pull down (recommended value is 1k
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
HDLCEX Interface
HDLCEXTxClk
Transmit Clock
I
3.3V LVTTL
HDLCEXTxFS
Transmit Frame Synchronization
I
3.3V LVTTL
HDLCEXTxDataA
Transmit Data port A
O
3.3V LVTTL
HDLCEXTxDataB
Transmit Data port B
O
3.3V LVTTL
HDLCEXRxClk
Receive Clock
I
3.3V LVTTL
HDLCEXRxFS
Receive Frame Synchronization
I
3.3V LVTTL
HDLCEXRxDataA
Receive Data port A
I
3.3V LVTTL
HDLCEXRxDataB
Receive Data port B
I
3.3V LVTTL
[HDLCEXTxEnA]
Transmit Enable port A
O
5V tolerant
3.3V LVTTL
[HDLCEXTxEnB]
Transmit Enable port B
O
5V tolerant
3.3V LVTTL
Ethernet Interface
EMC0MDClk
Management Data Clock. The MDClk is sourced to the
PHY. Management information is transferred
synchronously with respect to this clock (MII, RMII, and
SMII).
O
5V tolerant
3.3V LVTTL
EMC0MDIO
Management Data Input/Output is a bidirectional signal
between the Ethernet controller and the PHY. It is used to
transfer control and status information (MII, RMII, and
SMII).
I/O
5V tolerant
3.3V LVTTL
1, 4
EMC0TxD0[EMC0Tx0D0][EMC0Tx0D]
EMC0TxD1[EMC0Tx0D1][EMC0Tx1D]
EMC0TxD2[EMC0Tx1D0]
EMC0TxD3[EMC0Tx1D1]
Transmit Data. A nibble wide data bus towards the net.
The data is synchronous with PHY0TxClk
(MII 0[RMII 0 and 1][SMII 0, 1, 2, and 3]).
O
3.3V LVTTL
EMC0TxEn[EMC0Tx0En][EMC0Sync]
Transmit Enable. This signal is driven by EMAC2 to the
PHY. Data is valid during the active state of this signal.
Deassertion of this signal indicates end of frame
transmission. This signal is synchronous with PHYTxClk
(MII 0[RMII 0]).
or
SMII Sync.
O
3.3V LVTTL
EMC0TxErr[EMC0Tx1En]
Transmit Error. This signal is generated by the Ethernet
controller, is connected to the PHY and is synchronous
with the PHY0TxClk. It informs the PHY that an error was
detected (MII 0).
or
Transmit Enable [RMII 1].
O
5V tolerant
3.3V LVTTL
相关PDF资料 |
PDF描述 |
|---|---|
| PowerNP NPe405 | 32-Bit Embedded Processor(32位嵌入式处理器（应用于网络方面，提供高性价比）) |
| PowerPC 401GF | 32-bit RISC Embedded Controllers(32位RISC结构嵌入式控制器) |
| PowerPC 403GA | 32-bit RISC Embedded Controllers(32位RISC结构嵌入式控制器) |
| PowerPC 403GB | 32-bit RISC Embedded Controllers(32位RISC结构嵌入式控制器) |
| PowerPC 403GC | 32-bit RISC Embedded Controllers(32位RISC结构嵌入式控制器) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| POWERPAC-B | 制造商:IAR Systems 功能描述:PowerPac |
| POWERPAC-S | 制造商:IAR Systems 功能描述:PowerPac |
| POWERPAT PLUS | 制造商:Fluke Electronics 功能描述:SOFTWARE PAT |
| POWERPATPLUS | 制造商:Fluke Electronics 功能描述:Fluke Powerpat Plus |
| POWERPLUG15W | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:AC/DC POWER SUPPLY |
发布紧急采购，3分钟左右您将得到回复。