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参数资料
| 型号： | PPC440GR-3BB533CZ |
| 厂商： | APPLIEDMICRO INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 533 MHz, RISC PROCESSOR, PBGA456 |
| 封装： | 35 X 35 MM, PLASTIC, BGA-456 |
| 文件页数： | 4/88页 |
| 文件大小： | 1177K |
| 代理商： | PPC440GR-3BB533CZ |
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12
AMCC Proprietary
Revision 1.19 – May 07, 2008
Preliminary Data Sheet
440GR – PPC440GR Embedded Processor
PCI Interface
The PCI interface allows connection of PCI devices to the PowerPC processor and local memory. This interface is
designed to Version 2.2 of the PCI Specification and supports 32- bit PCI devices.
Reference Specifications:
PowerPC CoreConnect Bus (PLB) Specification Version 3.1
PCI Specification Version 2.2
PCI Bus Power Management Interface Specification Version 1.1
Features include:
PCI 2.2
– Frequency to 66MHz
– 32-bit bus
PCI Host Bus Bridge or an Adapter Device's PCI interface
Internal PCI arbitration function, supporting up to six external devices, that can be disabled for use with an
external arbiter
Support for Message Signaled Interrupts
Simple message passing capability
Asynchronous to the PLB
PCI Power Management 1.1
PCI register set addressable both from on-chip processor and PCI device sides
Ability to boot from PCI bus memory
Error tracking/status
Supports initiation of transfer to the following address spaces:
– Single beat I/O reads and writes
– Single beat and burst memory reads and writes
– Single beat configuration reads and writes (type 0 and type 1)
– Single beat special cycles
DDR SDRAM Memory Controller
The Double Data Rate (DDR) SDRAM memory controller supports industry standard discrete devices. Up to four
256MB logical banks are supported in limited configurations. Global memory timings, address and bank sizes, and
memory addressing modes are programmable.
Features include:
Registered and non-registered industry standard discrete devices
32-bit memory interface with optional 8-bit ECC (SEC/DED)
Sustainable 1.1GB/s peak bandwidth at 133MHz
SSTL_2 logic
1 to 4 chip selects
CAS latencies of 2, 2.5 and 3 supported
DDR200/266 support
Page mode accesses (up to eight open pages) with configurable paging policy
Programmable address mapping and timing
Hardware and software initiated self-refresh
Power management (self-refresh, suspend, sleep)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PPC440GR-3JA333C | 制造商:AppliedMicro 功能描述: |
| PPC440GR-3JA400C | 制造商:AppliedMicro 功能描述: |
| PPC440GR-3JA533C | 制造商:AppliedMicro 功能描述: |
| PPC440GR-3JA667C | 制造商:AppliedMicro 功能描述: |
| PPC440GR-3JB333C | 制造商:AppliedMicro 功能描述: |
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