- 您现在的位置：买卖IC网 > PDF目录224791 > PPC440GR-3BB533CZ (APPLIEDMICRO INC) 32-BIT, 533 MHz, RISC PROCESSOR, PBGA456 PDF资料下载
参数资料
| 型号： | PPC440GR-3BB533CZ |
| 厂商： | APPLIEDMICRO INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 533 MHz, RISC PROCESSOR, PBGA456 |
| 封装： | 35 X 35 MM, PLASTIC, BGA-456 |
| 文件页数： | 52/88页 |
| 文件大小： | 1177K |
| 代理商： | PPC440GR-3BB533CZ |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页当前第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页
56
AMCC Proprietary
Revision 1.19 – May 07, 2008
Preliminary Data Sheet
440GR – PPC440GR Embedded Processor
External Slave Peripheral Interface
DMAAck0:3
Used by the PPC440GR to indicate that data transfers have
occurred.
O
Multiplex
DMAReq0:3
Used by slave peripherals to indicate they are prepared to
transfer data.
I
Multiplex
1
EOT0:3/TC0:3
End Of Transfer/Terminal Count.
I/O
Multiplex
1
PerAddr02:07
Peripheral address bus used by PPC440GR when not in
external master mode, otherwise used by external master.
I/O
3.3V LVTTL
1, 2
PerAddr08:31
Peripheral address bus used by PPC440GR when not in
external master mode, otherwise used by external master.
I/O
3.3V LVTTL
PerBLast
Used by either the peripheral controller, DMA controller, or
external master to indicates the last transfer of a memory
access.
I/O
3.3V LVTTL
1, 4
PerCS0:5
External peripheral device select.
O
3.3V LVTTL
2
PerData00:15
Peripheral data bus used by PPC440GR when not in external
master mode, otherwise used by external master.
Note: PerData00 is the most significant bit (msb) on this bus.
I/O
3.3V LVTTL
1
PerOE
Used by either peripheral controller or DMA controller
depending upon the type of transfer involved. When the
PPC440GR is the bus master, it enables the selected device to
drive the bus.
O3.3V LVTTL
2
PerReady
Used by a peripheral slave to indicate it is ready to transfer
data.
I3.3V LVTTL
PerR/W
Used by the PPC440GR when not in external master mode, as
output by either the peripheral controller or DMA controller
depending upon the type of transfer involved. High indicates a
read from memory, low indicates a write to memory.
Otherwise, it used by the external master as an input to
indicate the direction of transfer.
I/O
3.3V LVTTL
1, 2
PerWBE0:1
External peripheral data bus byte enables.
I/O
3.3V LVTTL
1, 2
PerErr
External Error. Used as an input to record external slave
peripheral errors.
I/O
3.3V LVTTL
1
Table 9. Signal Functional Description (Sheet 4 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω to 3.3V)
3. Must pull down (recommended value is 1k
Ω)
4. If not used, must pull up (recommended value is 3k
Ω to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
相关PDF资料 |
PDF描述 |
|---|---|
| PPC440GRX-STA400TZ | 32-BIT, 400 MHz, RISC PROCESSOR, PBGA680 |
| PPCM08DNNNN920 | 8 CONTACT(S), PLASTIC, MALE, CIRCULAR CONNECTOR, CRIMP, PLUG |
| PRAF06ANNNN91502 | 6 CONTACT(S), ALUMINUM ALLOY/COPPER ALLOY/COPPER-ZINC ALLOY, CIRCULAR CONNECTOR, CRIMP |
| PRAF06ANNNN915 | 6 CONTACT(S), ALUMINUM ALLOY/COPPER ALLOY/COPPER-ZINC ALLOY, CIRCULAR CONNECTOR, CRIMP |
| PRAF08ANNNN91502 | 8 CONTACT(S), ALUMINUM ALLOY/COPPER ALLOY/COPPER-ZINC ALLOY, CIRCULAR CONNECTOR, CRIMP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PPC440GR-3JA333C | 制造商:AppliedMicro 功能描述: |
| PPC440GR-3JA400C | 制造商:AppliedMicro 功能描述: |
| PPC440GR-3JA533C | 制造商:AppliedMicro 功能描述: |
| PPC440GR-3JA667C | 制造商:AppliedMicro 功能描述: |
| PPC440GR-3JB333C | 制造商:AppliedMicro 功能描述: |
发布紧急采购，3分钟左右您将得到回复。