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参数资料
| 型号： | PPC440GR-3BB533CZ |
| 厂商： | APPLIEDMICRO INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 533 MHz, RISC PROCESSOR, PBGA456 |
| 封装： | 35 X 35 MM, PLASTIC, BGA-456 |
| 文件页数： | 84/88页 |
| 文件大小： | 1177K |
| 代理商： | PPC440GR-3BB533CZ |
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AMCC Proprietary
85
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
Revision 1.19 – May 07, 2008
Initialization
The PPC440GR provides the option for setting initial parameters based on default values or by reading them from
a slave PROM attached to the IIC0 bus (see “Serial EEPROM” below). Some of the default values can be altered
by strapping on external pins (see “Strapping” below).
Strapping
While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable certain default
initial conditions prior to PPC440GR start-up. The actual capture instant is the nearest reference clock edge before
the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0)
resistors to select the desired default conditions. These pins are used for strap functions only during reset.
Following reset they are used for normal functions. The signal names assigned to the pins for normal operation are
shown in parentheses following the pin number.
Note: To isolate the strapping pins, the ExtReset signal may be used as a buffer enable or multiplexer select.
The following table lists the strapping pins along with their functions and strapping options:
Serial EEPROM
During reset, initial conditions other than those obtained from the strapping pins can be read from a ROM device
connected to the IIC0 port. At the de-assertion of reset, if the bootstrap controller is enabled, the PPC440GR
sequentially reads 16B from the ROM device on the IIC0 port and sets the SDR0_SDSTP0, SDR0_SDSTP1,
SDR0_SDSTP2 and SDR0_SDSTP3 registers accordingly.
The initialization settings and their default values are covered in detail in the PowerPC 440GR User’s Manual.
Table 27. Strapping Pin Assignments
Function
Option
Ball Strapping
R25
(UART0_DCD)
U26
(UART0_DSR)
V26
(UART0_CTS)
Serial device is disabled. Each of the six options (A–
F) is a combination of boot source, boot-source
width, and clock frequency specifications. Refer to
the IIC Bootstrap Controller chapter in the
PPC440GR Embedded Processor User’s Manual for
details.
A
000
B
001
C
010
D
011
E
100
F
110
Serial device is enabled. The option being selected is
the IIC0 slave address that will respond with
strapping data.
Note: If reading of configuration data from the serial
device fails, the PPC440GR defaults to configuration
X.
G (0xA8)
101
H (0xA4)
111
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PPC440GR-3JA333C | 制造商:AppliedMicro 功能描述: |
| PPC440GR-3JA400C | 制造商:AppliedMicro 功能描述: |
| PPC440GR-3JA533C | 制造商:AppliedMicro 功能描述: |
| PPC440GR-3JA667C | 制造商:AppliedMicro 功能描述: |
| PPC440GR-3JB333C | 制造商:AppliedMicro 功能描述: |
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