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参数资料
| 型号： | PSD913F1V-12B81I |
| 厂商： | 意法半导体 |
| 英文描述： | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| 中文描述： | Flash在系统可编程ISP的外设的8位微控制器 |
| 文件页数： | 61/94页 |
| 文件大小： | 476K |
| 代理商： | PSD913F1V-12B81I |
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PSD9XX Family
Preliminary Information
60
Port C Pin
JTAG Signals
Description
PC0
TMS
Mode Select
PC1
TCK
Clock
PC3
TSTAT
Status
PC4
TERR
Error Flag
PC5
TDI
Serial Data In
PC6
TDO
Serial Data Out
Table 34. JTAG Port Signals
The
PSD9XX
Functional
Blocks
(cont.)
9.5.3.4 Reset of Flash Erase and Programming Cycles (PSD934F2 and PSD954F2)
An external reset on the RESET pin will also reset the internal Flash memory state
machine. When the Flash is in programming or erase mode, the RESET pin will terminate
the programming or erase operation and return the Flash back to read mode in tNLNH-A
(minimum 25 s) time.
9.6 Programming In-Circuit using the JTAG Interface
The JTAG interface on the PSD9XX can be enabled on Port C (see Table 34). All
memory (Flash and Secondary Flash Block), PLD logic, and PSD configuration bits may be
programmed through the JTAG interface. A blank part can be mounted on a printed circuit
board and programmed using JTAG.
The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional
signals, TSTAT and TERR, are optional JTAG extensions used to speed up program and
erase operations.
*SR_cod bit in the VM Register are always cleared to zero on power on or warm reset.
**
Port Configuration
Power On Reset
Warm Reset
Power Down Mode
MCU I/O
Input Mode
Unchanged
PLD Output
Valid after internal
Valid
Depend on inputs to
PSD configuration
PLD (address are
bits are loaded
blocked in PD mode)
Address Out
Tri-stated
Not defined
Data Port
Tri-stated
Table 33. Status During Power On Reset, Warm Reset and Power Down Mode
Register
Power On Reset
Warm Reset
Power Down Mode
PMMR0, 2
Cleared to “0”
Unchanged
VM Register*
Initialized based on
Unchanged
the selection in
PSDsoft
Configuration Menu.
All other registers
Cleared to “0”
Unchanged
By default, on a blank PSD (as shipped from factory or after erasure), four pins on Port C
are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO.
See Application Note 54 for more details on JTAG In-System-Programming.
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| PSD913F1V-12J | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12JI | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12M | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD933212JIT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PSD913F1V-12J | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12JI | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12M | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12MI | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12U | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
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