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| 型号： | PWL6030B1AACMR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA187 |
| 封装： | 7 X 7 MM, 0.40 MM PITCH, GREEN, FCBGA-187 |
| 文件页数： | 24/97页 |
| 文件大小： | 937K |
| 代理商： | PWL6030B1AACMR |
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SWCS045B
– SEPTEMBER 2010 – REVISED JUNE 2011
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT CONSUMPTION, WAIT-ON STATE
VBAT = 3.8 V
20
30
A
CURRENT CONSUMPTION, SLEEP STATE
VBACKUP = 0 V, VBAT = 3.8V
VANA = 0 V, VAUX1 = 0 V, VAUX2
= 0 V, VAUX3 = 0 V, VCXIO = 0 V,
VDAC = 0 V VMMC = 0 V, VPP = 0
V, VBRTC = 1.8 V, VRTC = 0V,
VUSB = 0 V, VUSIM = 0 V, V1V29 =
0 V, V1V8 = 1.8 V, V2V1 = 0 V,
VCORE1 = 0 V, VCORE2 = 0 V,
V1V8 and VMEM enabled, no load
110
A
VCORE3 = 0 V, VMEM = 0 V
RC6MHZ = OFF, CLK32KG = OFF,
CLK32KAUDIO = OFF VBG = ON,
VBATMIN_HI = OFF, TMP = OFF,
FG = OFF EPROM Features:
BSI_ISOURCE = OFF,
BAT_DET_EN = OFF, VMEM = 1.35
V
The following table describes the digital input signal electrical parameters.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PWRON, RPWRON
Low-level input voltage VIL-related
–0.3
0
0.35
× VBAT
V
to VBAT/VDD
High-level input voltage VIH-related
VBAT + 0.3
≤
0.65
× VBAT
VBAT
V
to VBAT/VDD
5.5
BOOT0, BOOT1, BOOT2, BOOT3, CHRG_EXTCHRG_STATZ, GPADC_START, MMC, MSECURE, NRESWARM, OSC32KIN, PREQ1,
PREQ2A, PREQ2B, PREQ2C, PREQ3, SIM, TESTEN
Low-level input voltage VIL-related
–0.3
0
0.35
× VR
V
to VIO or VRTC
High-level input voltage VIH-related
0.65
× VR
VR
VR + 0.3
V
to VIO or VRTC
CTLI2C_SCL, CTLI2C_SDA, SRI2C_SCL, SRI2C_SDA
Low-level input voltage VIL-related
–0.3
0
0.3
× VIO
V
to VIO
High-level input voltage VIH-related
0.7
× VIO
VIO
VIO + 0.3
V
to VIO
Hysteresis
0.1
× VIO
V
1.2-V SPECIFIC RELATED I/Os: PREQ3(1)(2)
Low-level input voltage VIL-related
–0.3
0
0.3
× VIO
V
to VIO
High-level input voltage VIH-related
0.7
× VIO
VIO
VIO + 0.3
V
to VIO
(1)
PREQ3 can be programmed for two different input supplies (1.2/1.8 V) and, as such, has a configurable input threshold.
(2)
Applying 1.8-V input logic on the PREQ3 ball when the 1.2-V supply mode is selected does not damage the PREQ3 input buffer.
Nevertheless, because the threshold is reduced to its 1.2-V configuration, the input buffer is more sensitive to the low 1.8-V logic level.
The following table describes the digital output signal electrical parameters.
PARAMETER(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REGEN1, REGEN2
Low-level output voltage VOL
IOL = 100 A
0
0.1
× VBAT
0.2
× VBAT
V
High-level output voltage VOH
IOH = 100 A
0.8
× VBAT
0.9
× VBAT
VBAT
V
BATREMOVAL, CLK32KAO, CLK32KG, INT, CHRG_EXTCHRG_ENZ, NRESPWRON, PWM1, PWM2, SYSEN
(1)
All output signals are guaranteed low when VRTC is not available, especially REGEN1, REGEN2, and SYSEN, all three of which control
some external power resources.
30
Copyright
2010–2011, Texas Instruments Incorporated
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