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参数资料
| 型号： | PWL6030B1AACMR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA187 |
| 封装： | 7 X 7 MM, 0.40 MM PITCH, GREEN, FCBGA-187 |
| 文件页数： | 71/97页 |
| 文件大小： | 937K |
| 代理商： | PWL6030B1AACMR |
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SWCS045B
– SEPTEMBER 2010 – REVISED JUNE 2011
The ACA comparators and 16-
A current source can be enabled or disabled by the VBUS wake-up comparator
until the first I2C write access to the OTG corresponding registers. Note that ACA feature is controlled by the
VBUS wake-up comparator only when NRESPWRON signal is low.
The following pullup and pulldown resistors and current sinks/sources can be connected to the VBUS line:
VBUS_CHRG_VBAT bit enables a VBUS 2-k
Ω pullup to the VBAT supply.
VBUS_CHRG_PMID bit enables a VBUS 2-k
Ω pullup to the CHRG_PMID supply.
VBUS_DISCHRG bit enables a VBUS 10-k
Ω pulldown.
VBUS_IADP_SRC bit enables a VBUS 1.4-mA current source on the VANA supply.
VBUS_IADP_SINK bit enables a VBUS 1.5-mA current sink.
RA_BUS_IN resistor is present permanently and is a combination of all parallel resistor bridges implemented
on VBUS in the various IPs such as backup battery, OTG, and charger.
RVBUS_LKG represents the TWL6030 internal leakage.
Related to the OTG 1.3 revision, four comparators supplied on the VANA regulator are implemented to detect
VBUS line voltage level.
In the OTG 2.0 revision, only one comparator is required for the session valid detection (VOTG_SESS_VLD)
supplied also on the VANA domain. In addition the VA_VBUS_VLD comparator can be used to detect a possible
VBUS short-circuit condition.
The TWL6030 device embeds the OTG 2.0 optional features related to the VBUS ADP probing and sensing, via
two additional comparators supplied on VANA (VADP_PRB, and VDAP_SNS).
Seven comparators allow detection of the four OTG 1.3 and the three OTG 2.0 debounced interrupts:
VA_VBUS_VLD (OTG 1.3/OTG 2.0)
– fixed 30 ms debouncing
VB_SESS_VLD (OTG 1.3)
– fixed 30 ms debouncing
VA_SESS_VLD (OTG 1.3)
– fixed 30 ms debouncing
VB_SESS_END (OTG 1.3)
– fixed 30 ms debouncing
VOTG_SESS_VLD (OTG 2.0)
– fixed 30 ms debouncing
VADP_PRB (OTG 2.0)
– fixed 2x 30 s debouncing
VADP_SNS (OTG 2.0)
– fixed 2x 30 s debouncing
It is possible to use the GPADC to monitor the voltage on the VBUS line (channel 10). A 6.875-V maximum
voltage on the VBUS line corresponds to a 1.25-V maximum dynamic at the input stage of the GPADC converter,
allowing a 6.0-V maximum measurement. For more information, see GENERAL-PURPOSE ADC .
NOTE
If the system switches off, VUSB stays on if VBUS is still connected.
When NRESPWRON is released, only software accesses enable the regulator, if not previously
enabled by the VBUS wake-up comparator in PRECHARGE state.
The VUSB regulator is a dual input supply LDO. The VUSB regulator enable is independent of
the overvoltage condition.
When a VBUS overvoltage condition occurs, the CHRG_PMID input switch is automatically
opened, protecting the VUSB LDO from possible overvoltage stresses.
When neither the VBAT nor PMID input supply is selected, the VUSB LDO cannot output a
proper voltage, even if its control enable is set (see the VUSB_CFG_TRANS register).
Software should keep monitoring the VBUS overvoltage condition and turn off the VUSB
regulator when necessary.
The VBUS detection mechanism works only when VANA supply is present:
–
TWL6030 SLEEP state
– VANA should remain active.
–
TWL6030 ACTIVE state
– VANA is always on.
For ADP detection, software can use the TWL6030 embedded mechanism or directly use the
output of the comparators with their associated interrupts.
Copyright
2010–2011, Texas Instruments Incorporated
73
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