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参数资料
| 型号： | QL3004 |
| 厂商： | QuickLogic Corp. |
| 英文描述： | pASIC 3 FPGA Family High Performance and High Density with Low Cost and Complete Flexibiltiy(具有低成本和充分灵活性的高性能和高密度的pASIC 3现场可编程门阵列) |
| 中文描述： | 帕希奇3 FPGA系列高性能与高密度的低成本和完整Flexibiltiy（具有低成本和充分灵活性的高性能和高密度的帕希奇3现场可编程门阵列） |
| 文件页数： | 5/10页 |
| 文件大小： | 254K |
| 代理商： | QL3004 |
7-5
pASIC 3 FPGA
TM
Family
FIGURE 4. 4-Layer Metal Reduces Die Sizes
The complete pASIC 3 logic cell consists of two 6-
input AND gates, four two-input AND gates, six two-
to-one multiplexers and one D flip-flop with
asynchronous set and reset controls. The cell has a
fan-in of 29 (including register control lines) and fits a
wide range of functions with up to 16 simultaneous
inputs. The high logic capacity and fan-in of the logic
cell accommodate many user functions with a single
level of logic delay (resulting in high performance)
while other architectures require two or more levels
of delay. Examples of functions which can be
implemented with a single logic cell delay include:
one 16-input AND gate, two 6-input AND gates plus
two 4-input AND gates, two 6-input AND gates plus
two 2:1 or one one 4:1 multiplexer, one 5-input
XOR gate, one 3-input XOR and one 2-input XOR,
and numerous sum-of-products functions with up to
16 inputs or 16 product terms.
The D-type flip-flop can also be configured to provide
J-K, S-R, or T-type functions. Two independent set
and reset inputs can asynchronously control the
output condition. Additional flip-flops can be built
using the multiplexers in the logic cell. In general, up
to three independent flip-flops are available for every
two logic cells. The combination of wide gating
capability, a built-in register, and the capability to
build additional registers makes the logic cell
particularly well suited to the design of high-speed
state machines, shift registers, encoders, decoders,
arbitration and arithmetic logic, as well as a wide
variety of counters.
Figure 6 shows some of the possible configurations
of the logic cell. Since all connections within the cell
are hard-wired, the various functions are available in
parallel. Thus very wide, complex functions are
implemented with the same cell speed (about 2ns) as
the much smaller "fragment" functions. Related and
unrelated functions can be packed into the same logic
cell, increasing effective density and gate utilization.
FIGURE 5. Logic Cell
FIGURE 6. Efficiency and High Performance
2-Layer Metal
4-Layer Metal
QS
A1
A2
A3
A4
A5
A6
OS
OP
B1
B2
C1
C2
MP
D1
D2
E1
E2
NP
NS
F1
F2
F3
F4
F5
F6
QC
AZ
OZ
QZ
NZ
FZ
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