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参数资料
| 型号： | QLPXA263B1C400 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, PBGA294 |
| 封装： | 13 X 13 MM, 1.4MM PITCH, PLASTIC, TPBGA-294 |
| 文件页数： | 2/44页 |
| 文件大小： | 1302K |
| 代理商： | QLPXA263B1C400 |
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Package Information
10
Intel PXA255 Processor Electrical, Mechanical, and Thermal Specification
SDCKE[1]
OC
SDRAM and/or Synchronous Static Memory clock
enable. (output) Connect to the clock enable pins of
SDRAM. It is deasserted during sleep. SDCKE[1] is
always de-asserted upon reset. The memory controller
provides control register bits for de-assertion.
Driven low
SDCLK[0]
OC
Synchronous Static Memory clock. (output) Connect to
the clock (CLK) pins of SMROM. It is driven by either the
internal memory controller clock, or the internal memory
controller clock divided by 2. At reset, all clock pins are
free running at the divide-by-2 clock speed and may be
turned off via free-running control register bits in the
memory controller. The memory controller also provides
control register bits for clock division and deassertion of
each SDCLK pin. SDCLK[0] control register assertion bit
defaults to on if the boot-time static memory bank 0 is
configured for SMROM.
SDCLK[1]
OCZ
SDRAM Clocks (output) Connect SDCLK[1] and
SDCLK[2] to the clock pins of SDRAM in bank pairs 0/1
and 2/3, respectively. They are driven by either the
internal memory controller clock, or the internal memory
controller clock divided by 2. At reset, all clock pins are
free running at the divide-by-2 clock speed and may be
turned off via free-running control register bits in the
memory controller. The memory controller also provides
control register bits for clock division and de-assertion of
each SDCLK pin. SDCLK[2:1] control register assertion
bits are always de-asserted upon reset.
Driven Low
SDCLK[2]
OC
Driven Low
nCS[5]/
GPIO[33]
ICOCZ
Static chip selects. (output) Chip selects to static
memory devices such as ROM and Flash. Individually
programmable in the memory configuration registers.
nCS[5:0] can be used with variable latency I/O devices.
Pulled High -
Note[1]
Note [4]
nCS[4]/
GPIO[80]
ICOCZ
nCS[3]/
GPIO[79]
ICOCZ
nCS[2]/
GPIO[78]
ICOCZ
nCS[1]/
GPIO[15]
ICOCZ
nCS[0]
ICOCZ
Static chip select 0. (output) Chip select for the boot
memory. nCS[0] is a dedicated pin.
Driven High
Note [4]
RD/nWR
OCZ
Read/Write for static interface. (output) Signals that the
current transaction is a read or write.
Driven Low
Holds last state
RDY/
GPIO[18]
ICOCZ
Variable latency I/O ready pin. (input) Notifies the
memory controller when an external bus device is ready
to transfer data.
Pulled High -
Note[1]
Note [3]
L_DD[8]/
GPIO[66]
ICOCZ
LCD display data. (output) Transfers pixel information
from the LCD controller to the external LCD panel.
Memory controller alternate bus master request.
(input) Allows an external device to request the system
bus from the memory controller.
Pulled High -
Note[1]
Note [3]
Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 2 of 9)
Pin Name
Type
Signal Descriptions
Reset State
Sleep State
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