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参数资料
| 型号： | QLPXA263B1C400 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, PBGA294 |
| 封装： | 13 X 13 MM, 1.4MM PITCH, PLASTIC, TPBGA-294 |
| 文件页数： | 44/44页 |
| 文件大小： | 1302K |
| 代理商： | QLPXA263B1C400 |
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Package Information
Intel PXA255 Processor Electrical, Mechanical, and Thermal Specification
9
Some of the processor pins can be connected to multiple signals. The GAFRn_m registers
determine the signal connected to the pin. Some signals can go to multiple pins. The signal must be
routed to one pin only by using the GAFRn_m registers. Because this is true, some pins are listed
twice—once in each unit that can use the pin. Not all peripherals can be used simutaneously in one
design because different peripherals share the same pins.
Table 2. Processor Pin Types
Type
Function
IC
CMOS input
OC
CMOS output
OCZ
CMOS output, Hi-Z
ICOCZ
CMOS bidirectional, Hi-Z
IA
Analog Input
OA
Analog output
IAOA
Analog bidirectional
SUP
Supply pin (either VCC or VSS)
Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 1 of 9)
Pin Name
Type
Signal Descriptions
Reset State
Sleep State
Memory Controller Pins
MA[25:0]
OCZ
Memory address bus. (output) Signals the address
requested for memory accesses.
Driven Low
MD[15:0]
ICOCZ
Memory data bus. (input/output) Lower 16 bits of the
data bus.
Hi-Z
Driven Low
MD[31:16]
ICOCZ
Memory data bus. (input/output) Used for 32-bit
memories.
Hi-Z
Driven Low
nOE
OCZ
Memory output enable. (output) Connect to the output
enables of memory devices to control data bus drivers.
Driven High
Note [4]
nWE
OCZ
Memory write enable. (output) Connect to the write
enables of memory devices.
Driven High
Note [4]
nSDCS[3:0]
OCZ
SDRAM CS for banks 3 through 0. (output) Connect to
the chip select (CS) pins for SDRAM. For the PXA255
processor processor nSDCS0 can be Hi-Z, nSDCS1-3
cannot.
Driven High
Note [5]
DQM[3:0]
OCZ
SDRAM DQM for data bytes 3 through 0. (output)
Connect to the data output mask enables (DQM) for
SDRAM.
Driven Low
nSDRAS
OCZ
SDRAM RAS. (output) Connect to the row address
strobe (RAS) pins for all banks of SDRAM.
Driven High
nSDCAS
OCZ
SDRAM CAS. (output) Connect to the column address
strobe (CAS) pins for all banks of SDRAM.
Driven High
SDCKE[0]
OC
Synchronous Static Memory clock enable. (output)
Connect to the CKE pins of SMROM. The memory
controller provides control register bits for de-assertion.
Driven Low
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