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参数资料
| 型号： | QLPXA263B1C400 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, PBGA294 |
| 封装： | 13 X 13 MM, 1.4MM PITCH, PLASTIC, TPBGA-294 |
| 文件页数： | 27/44页 |
| 文件大小： | 1302K |
| 代理商： | QLPXA263B1C400 |
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Electrical Specifications
Intel PXA255 Processor Electrical, Mechanical, and Thermal Specification
33
4.7.5
Sleep Mode Timing
Sleep mode is asserted internally; and asserts the nRESET_OUT and PWR_EN signals. The
sequence indicated in Figure 6, “Sleep Mode Timing” on page 34 and detailed in Figure 18, “Sleep
Mode Timing Specifications” on page 34 is the required timing parameters for sleep mode.
Figure 5. GPIO Reset Timing
Table 17. GPIO Reset Timing Specifications
Symbol
Description
Min
Typical
Max
Units
tA_GP[1]
Minimum assert time of GP[1]1 in
3.6864MHz input clock cycles
4
cycles
tDHW_OUT_A
Delay between GP[1] asserted and
nRESET_OUT asserted in 3.6864 MHz
input clock cycles
3
8
cycles
tDHW_OUT
Delay between nRESET_OUT asserted
and nRESET_OUT de-asserted, run or
turbo mode2
1.28
6.5
s
tDHW_OUT_F
Delay between nRESET_OUT asserted
and nRESET_OUT de-asserted, during
frequency change sequence3
1.28
360
s
tDHW_NCS0
Delay between nReset_Out de-asserted
and nCS0 asserted
150.69
—
390
ns
NOTES:
1. GP[1] is not recognized as a reset source again until configured to do so in software. Software should
check the state of GP[1] before configuring as a reset to ensure no spurious reset is generated.
2. Time is 512*N processor clock cycles plus up to 4 cycles of the 3.6864-MHz input clock.
3. Time during the frequency change sequence depends on the state of the PLL lock detector at the
assertion of GPIO reset. The lock detector has a maximum time of 350s plus synchronization.
GP[1]
nRESET_OUT
t
DHW_OUT
t
A_GP[1]
t
DHW_OUT_A
Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is
deasserted or the application processor will enter Sleep Mode
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