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参数资料
| 型号： | R0K561664S001BE |
| 厂商： | Renesas Electronics America |
| 文件页数： | 11/50页 |
| 文件大小： | 0K |
| 描述： | KIT STARTER FOR H8SX/1651 |
| 产品培训模块： | H8S Product Overview H8S Architecture Overview Electromagnetic Noise Reduction Techniques Part 1 |
| 标准包装： | 1 |
| 系列： | H8® |
| 类型： | MCU |
| 适用于相关产品： | H8SX/1651 |
| 所含物品： | CPU 板，LCD 显示模块，E10A 仿真器，缆线，快速入门指南和 CD-ROM |
| 相关产品： | R5F61668RN50FPV-ND - IC H8SX/1668 MCU FLASH 144LQFP R5F61664RN50FPV-ND - IC H8SX/1664 MCU FLASH 144LQFP DF61664W50FPV-ND - IC H8SX/1664 MCU FLASH 144-LQFP DF61663W50FPV-ND - IC H8SX/1663 MCU FLASH 144-LQFP DF61664N50FPV-ND - MCU 3V 512K 144-LQFP DF61663N50FPV-ND - IC H8SX/1663 MCU FLASH 144LQFP |
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9
On-chip Peripheral s : Timers
■ Timer s
? Rich suite of 8-bit and
16-bit multifunction,
multipurpose timers
– Input capture, output
Select clock
Internal clock
φ
φ /2
Clock
Ba s e cycle compare match A
Internal data bu s
Bu s interface
compare, auto reload,
event counter, up/down
counter, interval timer,
and sleep mode timer
? 3-phase Motor Control
Timer
PWX0
PWX1
Control
logic
Fine–adju s tment pul s e addition
Ba s e cycle compare match B
Fine–adju s tment pul s e addition
Ba s e cycle overflow
Comparator
A
Comparator
B
DACNT
DADRA
DADRB
– 2-phase encoder with
up/down count
capability
– Suitable for motor
Legend:
DACR
Module data bu s
control apps
? Asynchronous Event
Counter (AEC)
– Counts events even when
system clock is disabled
for power savin g
? Watchdo g timer (W D T)
with independent RC
circuit for g reater safety
DACR: PWM D/A control regi s ter
DADRA: PWM D/A data regi s ter A
DADRB: PWM D/A data regi s ter B
DACNT: PWM D/A counter
H8/Tiny 14-bit PWM Timer Block Diagram
SUBC K /32
SUBC K /64
? 10-bit or 14-bit
P ulse Width Modulation
( P WM) timer with
32 K OVI (IRQ15)
(Interrupt
reque s t s ignal)
Counter
Clock
Clock
Select
SUBC K /128
SUBC K /256
Internal clock
ripple-reduction feature
– Can be used as a D /A
converter by addin g an
external low-pass filter
? Real-Time Clock (RTC):
seconds, minutes, hours,
TCNT32K
Module bu s
TCR32K
Bus
Interface
days and weeks
TK32K
H8S 32K Sleep Mode Timer Block Diagram
■ Programmable Pul s e G enerator (PP G ) / Timing Pattern Controller (TPC)
? Arbitrary waveform patterns are stored in memory and g enerated on
output pins with the PP G or T P C in conjunction with a timer and D MA
? P rovides 8/16-bit pro g rammable pulse outputs usin g T P U as base
? Output tri gg er si g nals can be selected in 4-bit g roups
? Each g roup can operate both simultaneously and independently
? Output tri gg er si g nals can operate in parallel with D TC and D MAC
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