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参数资料
| 型号： | R0K561664S001BE |
| 厂商： | Renesas Electronics America |
| 文件页数： | 13/50页 |
| 文件大小： | 0K |
| 描述： | KIT STARTER FOR H8SX/1651 |
| 产品培训模块： | H8S Product Overview H8S Architecture Overview Electromagnetic Noise Reduction Techniques Part 1 |
| 标准包装： | 1 |
| 系列： | H8® |
| 类型： | MCU |
| 适用于相关产品： | H8SX/1651 |
| 所含物品： | CPU 板，LCD 显示模块，E10A 仿真器，缆线，快速入门指南和 CD-ROM |
| 相关产品： | R5F61668RN50FPV-ND - IC H8SX/1668 MCU FLASH 144LQFP R5F61664RN50FPV-ND - IC H8SX/1664 MCU FLASH 144LQFP DF61664W50FPV-ND - IC H8SX/1664 MCU FLASH 144-LQFP DF61663W50FPV-ND - IC H8SX/1663 MCU FLASH 144-LQFP DF61664N50FPV-ND - MCU 3V 512K 144-LQFP DF61663N50FPV-ND - IC H8SX/1663 MCU FLASH 144LQFP |
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11
On-chip Peripheral s : Data Transfer & Memory
■ DMA Controller (DMAC)
? Max. of 4 channels can be used
RD
HWR , LWR
RD
HWR , LWR
? D ual-address or sin g le-address
mode can be selected
? Supports Sin g le, Burst, Sequential,
A23 to A0
H8S/2633
Addre ss bu s
(Read)
D15 to D0
A23 to A0
H8S/2633
BUFFER
Addre ss bu s
Read (1 s t cycle)
D15 to D0
Idle and Repeat Transfer modes
? D ata can be transferred
in word or byte units
DACK
(Write)
A15 to A0
Write (2nd cycle)
Addre ss bu s
? Activation: internal interrupt,
external request, auto-request
■ Data Tran s fer Controller (DTC)
? Max. of 85 channels can be used
Single-Address Mode (Parallel read and write)
Interrupt
request
DTC
service
Dual-Address Mode (Two-cycle read and write)
DMA Controller Block Diagram
Source
Memory data
? Multiple transfers or multiple types of transfers
possible for one activation source
Interrupt
controller
request
Channel n
n+1
Destination
DMA Register
? Supports Sin g le, Burst, Chain and Repeat
Transfer modes
? D ata can be transferred in byte or word units
? Activation sources: interrupt and software
■ TFT-LCD Direct Drive (E x DMA)
? 16bpp D irect D rive of TFT-LC D panels
? P ixel Clock, V-sync, H-sync, D ata Enable
and VCOM driven
Data Transfer
Controller Chain
Transfer Mode
H8S/2378 MCU
32KB SRAM ? 512KB Fl as h
Flash
n+2
On-chip 1KB RAM
WR/
RD/
Addre ss Bu s
Source
Serial I/O
Destination
Memory
256 K x 16
SRAM
(Frame Buffer)
RGB
? Fully flexible for different panel sizes
and interface specifications
H8S CPU
Processing
ExDMA
Controller
Data Bu s
EDREQ
RGB
? H8S/2378 drives QVGA, WQVGA panels
QVGA
TFT-LCD
– WQVGA (480 x 272) driven at 116Hz
? H8SX/1668 drives VGA and WVGA
System
Peripherals
Timer
(TPU)
Pixel Clock
V s ync, H s ync, Enable
– WVGA (800 x 480) driven at 65Hz
? C P U core is li g htly loaded durin g LC D D irect D rive,
leavin g C P U core available for other system al g orithms
– H8S 6% loaded, H8SX 2% loaded
? Interleaved accesses allow frame buffer update for animation
TFT-LCD Direct Drive (ExDMA)
■ Data Fla s h with B G O
Memory Map
? Two blocks of 4KB each of D ata Flash
available for stora g e of non-volatile data
User Flash
(Application)
Time
? BGO (Back Ground Operation) allows
Erasin g or P ro g rammin g of D ata Flash
while executin g application code.
Data Flash
(Virtual EEPROM)
SRAM
Data
Flash
User
Flash
Read
Erase / Program
Read Read
Read
? Erase operation can be suspended automatically to
allow Readin g / P ro g rammin g of User or D ata Flash
Data Flash with BGO Diagram
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