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参数资料
| 型号： | R0K561664S001BE |
| 厂商： | Renesas Electronics America |
| 文件页数： | 8/50页 |
| 文件大小： | 0K |
| 描述： | KIT STARTER FOR H8SX/1651 |
| 产品培训模块： | H8S Product Overview H8S Architecture Overview Electromagnetic Noise Reduction Techniques Part 1 |
| 标准包装： | 1 |
| 系列： | H8® |
| 类型： | MCU |
| 适用于相关产品： | H8SX/1651 |
| 所含物品： | CPU 板，LCD 显示模块，E10A 仿真器，缆线，快速入门指南和 CD-ROM |
| 相关产品： | R5F61668RN50FPV-ND - IC H8SX/1668 MCU FLASH 144LQFP R5F61664RN50FPV-ND - IC H8SX/1664 MCU FLASH 144LQFP DF61664W50FPV-ND - IC H8SX/1664 MCU FLASH 144-LQFP DF61663W50FPV-ND - IC H8SX/1663 MCU FLASH 144-LQFP DF61664N50FPV-ND - MCU 3V 512K 144-LQFP DF61663N50FPV-ND - IC H8SX/1663 MCU FLASH 144LQFP |
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H8 Family of Microcontrollers
?
H 8 MCUs: Fully Upward Compatible
6
H8 C P Us are all CISC-based (Complex Instruction Set
Computation), developed to allow compatibility up and
down the various H8 series. This makes it easy to move
between the product lines in the H8 family.
The C P Us within the H8 family ran g e from 8-bit,
low-power optimized cores to full 32-bit hi g h-performance
H8SX MAC
87 instructions
9 address modes
H8S/2600 MAC
69 instructions
8 address modes
? Data bu s width extended to 32 bit s
? Enhanced memory operation s upport
? Enhanced addre ss mode s
? Enhanced bit operation in s truction
? Four MAC in s truction s added
cores that achieve 1MI P S/MHz.
H8S/2000
Benefits of H8 CPU co r es include:
? Most instructions execute in one clock cycle
? Built-in hardware MAC (H8S/2600 and H8SX only)
? Fast multipliers and dividers
? Enhanced memory addressin g schemes
(memory-to-memory access, one instruction)
? Advanced conditional branchin g instructions
? P owerful CISC instructions with small code size
65 instructions
8 address modes
H8/300H
64 instructions
8 address modes
H8/300L
57 instructions
8 address modes
? Multiple load/ s tore in s truction
? 8/16/32-bit arithmetic in s truction s
? Enhanced pu s h and pop in s truction
? Signed/un s igned MULT/DIV in s truction
? Signed/un s igned exten s ion in s truction
? Enhanced trap exception handling
? 8/16-bit arithmetic & logic in s truction s
? Un s igned MULT/DIV in s truction s
? Powerful bit manipulation in s truction s
H8 CPU Register Set
The C P Us within the H8 family are
General Registers
ER0
15
E0
0 7
R0H
0 7
R0L
0
desi g ned from the same re g ister set,
allowin g complete compatibility.
ER1
ER2
ER3
ER4
ER5
ER6
ER7 (SP)
E1
E2
E3
E4
E5
E6
E7
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R1L
R2L
R3L
R4L
R5L
R6L
R7L
H8/300L S erie s
use 8 g eneral-purpose re g isters as
8 and 16 bits. P C is 16 bits wide.
H8/300H S erie s
use 8 g eneral-purpose re g isters as
8, 16 and 32 bits. P C is 24 bits wide.
Control Registers
PC
31
23
15
0
H8 S /2000 S erie s
7 6 5 4 3 2 1 0
use 8 g eneral-purpose re g isters as
CCR
EXR
I UI H U N Z V C
7 6 5 4 3 2 1 0
T - - - - I2 I1 I0
8, 16 and 32 bits. P C is 24 bits wide.
H8 S /2600 S erie s
use 8 g eneral-purpose re g isters as
MAC Registers
63
Sign exten s ion
41
MACH
32
8, 16 and 32 bits. P C is 24 bits wide.
Hardware MAC.
MACL
31
0
H8 S X S erie s
Vector Base
Register (VBR)
31
12
(Re s erved)
0
use 8 g eneral-purpose re g isters as
8, 16 and 32 bits. P C is 32 bits wide.
Short Base
Register (SBR)
31
8
(Re s erved)
0
Hardware MAC. VBR and SBR
available.
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