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参数资料
| 型号： | R5F212BASDFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PQFP48 |
| 封装： | 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件页数： | 33/138页 |
| 文件大小： | 492K |
| 代理商： | R5F212BASDFP |
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215
4317K–AVR–03/2013
AT90PWM2/3/2B/3B
19.3.3.2
Manchester decoder
When configured in Manchester mode, the EUSART receiver is able to receive serial frame
using a 17-bit shift register, an edge detector and several data/control registers. The Manchester
decoder receives a frame from the RxD pin of the EUSART interface and loads the received
data in the EUSART data register (UDR and EUDR).
The bit order of the data bits in the frame is configurable to handle MSB or LSB first.
The polarity of the bi-phase start is not configurable. The start bit a logical ‘1’ (rising edge at bit
center).
The polarity of the stop bits is not configurable, the interface allows to read the 2 stops bits value
by software.
The Manchester decoder is enable when the EUSART is configured in Manchester mode and
the RXEN of USCRB set (global USART receive enable).
The number of data bits to be received can be configured with the URxS bits of EUCSRA
register.
The Manchester decoder provides a special mode where 16 or 17 data bits can be received. In
this mode the Manchester decoder can automatically detects if the seventeenth bit is Manches-
ter encoded or not (seventeenth data bit or first stop bit). If the receiver detects a valid data bit
(Manchester transition) during the seventeenth bit time of the frame, the receiver will process the
frame as a 17-bit frame lenght and set the F1617 bit of EUCSRC register.
In Manchester mode, the clock used for sampling the EUSART input signal is programmed by
the baudrate generator.
The edge detector of the Manchester decoder is based upon a 16 bits up/down counter which
maximum value can be configured through the MUBRRH and MUBRRL registers.
The maximum counter value is given by the following formula:
MUBRR[H:L]=F
CLKIO / (baud rate frequency)
MBURR[H:L] is used to calibrate the detect window of the start bit and to detect time overflow of
the other bits.
19.3.4
Double Speed Operation (U2X)
Double Speed Operation is controlled by U2X bit in UCSRA. See “Double Speed Operation
This mode of operation is not allowed in manchester bit coding.
Each ‘bit time’ in the Manchester serial frame is divided into two phases (See Figure 19-4). The
counter counts during the first phase and counts down during the second one. When the data bit
transition is detected, the counter memorises the N1 counter value and start counting down.
When the counter reaches the zero value, it starts counting up again and the N1/2 value allows
to open the next detection window. This detection window defines the time zone where the next
data bit edge is sampled.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| R5F212BASDFP#U0 | 制造商:Renesas Electronics Corporation 功能描述:MCU 16-Bit R8C CISC 96KB Flash 2.5V/3.3V/5V 64-Pin LQFP 制造商:Renesas Electronics Corporation 功能描述:MCU 16-bit R8C CISC 96KB Flash 2.5V/3.3V/5V 64-Pin LQFP |
| R5F212BASDFP#V0 | 功能描述:IC R8C/2B MCU FLASH 64LQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:R8C/2x/2B 标准包装:250 系列:56F8xxx 核心处理器:56800E 芯体尺寸:16-位 速度:60MHz 连通性:CAN，SCI，SPI 外围设备:POR，PWM，温度传感器，WDT 输入/输出数:21 程序存储器容量:40KB（20K x 16） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:6K x 16 电压 - 电源 (Vcc/Vdd):2.25 V ~ 3.6 V 数据转换器:A/D 6x12b 振荡器型:内部 工作温度:-40°C ~ 125°C 封装/外壳:48-LQFP 包装:托盘 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323 |
| R5F212BASDFP#V2 | 制造商:Renesas Electronics Corporation 功能描述:R8C/2B 96+2/7 64LQFP 10X10 -40 制造商:Renesas Electronics Corporation 功能描述:R8C/2B 96+2/7 64LQFP 10X10 -40 TO +85 - Trays 制造商:Renesas Electronics Corporation 功能描述:IC MCU 16BIT 96KB FLASH 64LQFP |
| R5F212BASDXXXFA | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:RENESAS MCU R8C FAMILY / R8C/2x SERIES |
| R5F212BASDXXXFP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:RENESAS MCU R8C FAMILY / R8C/2x SERIES |
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