参数资料
型号: R5F212BASDFP
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PQFP48
封装: 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件页数: 58/138页
文件大小: 492K
代理商: R5F212BASDFP
238
4317K–AVR–03/2013
AT90PWM2/3/2B/3B
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion
starts at the following rising edge of the ADC clock cycle. See “Changing Channel or Reference
Selection” on page 239 for details on differential conversion timing.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched
on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.
The actual sample-and-hold takes place 3.5 ADC clock cycles after the start of a normal conver-
sion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is
complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion
mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new
conversion will be initiated on the first rising ADC clock edge.
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures
a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold
takes place two ADC clock cycles after the rising edge on the trigger source signal. Three addi-
tional CPU clock cycles are used for synchronization logic.
In Free Running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high. For a summary of conversion times, see Table 21-1.
Figure 21-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Figure 21-5. ADC Timing Diagram, Single Conversion
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
Sample & Hold
ADIF
ADCH
ADCL
Cycle Number
ADEN
1
212
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
First Conversion
Next
Conversion
3
MUX and REFS
Update
MUX
and REFS
Update
Conversion
Complete
4
5
6
7
8
9
10
11
12
13
14
15
16
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
12
One Conversion
Next Conversion
3
Sample & Hold
MUX and REFS
Update
Conversion
Complete
MUX and REFS
Update
1
2
3
相关PDF资料
PDF描述
R5F212BASNFA 16-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PQFP48
R5F212ACSDFP 16-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PQFP48
R5F212BCSNFP 16-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PQFP48
R5F212BASNFP 16-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PQFP48
R5F212ACSNFP 16-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PQFP48
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