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| 型号： | R5F2138CFJFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | FLASH, 20 MHz, MICROCONTROLLER, PQFP80 |
| 封装： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件页数： | 27/30页 |
| 文件大小： | 483K |
| 代理商： | R5F2138CFJFP |
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ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
15.2.2
Registers
The Timer/Counter (TCNT0) and Output Compare Register (OCR0A) are 8-bit registers. Interrupt request (abbrevi-
ated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All interrupts are
individually masked with the Timer Interrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the
figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin. The
Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement)
its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is
referred to as the timer clock (clk
T0).
The double buffered Output Compare Register (OCR0A) is compared with the Timer/Counter value at all times.
The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency out-
put on the Output Compare pin (OC0A). See ”Output Compare Unit” on page 86. for details. The compare match
event will also set the Compare Flag (OCF0A) which can be used to generate an Output Compare interrupt
request.
15.3
Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the
Clock Select logic which is controlled by the Clock Select (CS02:0) bits located in the Timer/Counter Control Reg-
ister (TCCR0A). For details on clock sources and prescaler, see ”Timer/Counter0 and Timer/Counter1 prescalers”
15.4
Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 15-2 shows a
block diagram of the counter and its surroundings.
Figure 15-2. Counter Unit, block diagram.
Signal description (internal signals):
count
Increment or decrement TCNT0 by 1.
direction
Select between increment and decrement.
clear
Clear TCNT0 (set all bits to zero).
clk
Tn
Timer/Counter clock, referred to as clk
T0 in the following.
top
Signalize that TCNT0 has reached maximum value.
bottom
Signalize that TCNT0 has reached minimum value (zero).
Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock
(clk
T0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits
(CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be
accessed by the CPU, regardless of whether clk
T0 is present or not. A CPU write overrides (has priority over) all
counter clear or count operations.
DATA BUS
TCNTn
Control Logic
count
TOVn
(Int.Req.)
Clock Select
top
Tn
Edge
Detector
( From Prescaler )
clk
Tn
bottom
direction
clear
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