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参数资料
| 型号： | R5F2138CFJFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | FLASH, 20 MHz, MICROCONTROLLER, PQFP80 |
| 封装： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件页数： | 28/30页 |
| 文件大小： | 483K |
| 代理商： | R5F2138CFJFP |
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86
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter
Control Register (TCCR0A). There are close connections between how the counter behaves (counts) and how
waveforms are generated on the Output Compare output OC0A. For more details about advanced counting
sequences and waveform generation, see ”Modes of operation” on page 88.
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by the WGM01:0 bits.
TOV0 can be used for generating a CPU interrupt.
15.5
Output Compare Unit
The 8-bit comparator continuously compares TCNT0 with the Output Compare Register (OCR0A). Whenever
TCNT0 equals OCR0A, the comparator signals a match. A match will set the Output Compare Flag (OCF0A) at the
next timer clock cycle. If enabled (OCIE0A = 1 and Global Interrupt Flag in SREG is set), the Output Compare Flag
generates an Output Compare interrupt. The OCF0A Flag is automatically cleared when the interrupt is executed.
Alternatively, the OCF0A Flag can be cleared by software by writing a logical one to its I/O bit location. The Wave-
form Generator uses the match signal to generate an output according to operating mode set by the WGM01:0 bits
and Compare Output mode (COM0A1:0) bits. The max and bottom signals are used by the Waveform Generator
for handling the special cases of the extreme values in some modes of operation (See ”Modes of operation” on
Figure 15-3 shows a block diagram of the Output Compare unit.
Figure 15-3. Output Compare Unit, block diagram.
The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the nor-
mal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering
synchronizes the update of the OCR0 Compare Register to either top or bottom of the counting sequence. The
synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output
glitch-free.
The OCR0A Register access may seem complex, but this is not case. When the double buffering is enabled, the
CPU has access to the OCR0A Buffer Register, and if double buffering is disabled the CPU will access the OCR0A
directly.
OCFnx (Int.Req.)
= (8-bit Comparator )
OCRnx
OCnx
DATA BUS
TCNTn
WGMn1:0
Waveform Generator
top
FOCn
COMnx1:0
bottom
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相关代理商/技术参数 |
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| R5F2138CMDFD | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:The R8C/38M Group has data flash (1 KB × 4 blocks) with the background operation |
| R5F2138CMDFP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:The R8C/38M Group has data flash (1 KB × 4 blocks) with the background operation |
| R5F2138CMDFP#30 | 制造商:Renesas Electronics Corporation 功能描述:IC MCU 16BIT 128KB FLASH 80LQFP |
| R5F2138CMDFP#V0 | 制造商:Renesas Electronics Corporation 功能描述:IC MCU 16BIT 128KB FLASH 80LQFP |
| R5F2138CMDXXXFD | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:The R8C/38M Group has data flash (1 KB × 4 blocks) with the background operation |
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