参数资料
型号: R5F2L3ACCNFP
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100
封装: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件页数: 47/74页
文件大小: 959K
代理商: R5F2L3ACCNFP
52
2588F–AVR–06/2013
ATtiny261/461/861
rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described
If the low level on the interrupt pin is removed before the device has woken up then program
execution will not be diverted to the interrupt service routine but continue from the instruction fol-
lowing the SLEEP command.
9.3
Register Description
9.3.1
MCUCR – MCU Control Register
The MCU Register contains control bits for interrupt sense control.
Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 or INT1 if the SREG I-flag and the
corresponding interrupt mask are set. The level and edges on the external INT0 or INT1 pin that
activate the interrupt are defined in Table 9-2. The value on the INT0 or INT1 pin is sampled
before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one
clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an inter-
rupt. If low level interrupt is selected, the low level must be held until the completion of the
currently executing instruction to generate an interrupt.
9.3.2
GIMSK – General Interrupt Mask Register
Bit 7 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU
Control Register (MCUCR) define whether the external interrupt is activated on rising and/or fall-
ing edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even
if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is
executed from the INT1 Interrupt Vector.
Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU
Bit
7654
3
2
10
PUD
SE
SM1
SM0
ISC01
ISC00
MCUCR
Read/Write
R
R/W
R
R/W
Initial Value
0000
0
00
Table 9-2.
Interrupt 0 Sense Control
ISC01
ISC00
Description
0
The low level of INT0 or INT1 generates an interrupt request.
0
1
Any logical change on INT0 or INT1 generates an interrupt request.
1
0
The falling edge of INT0 or INT1 generates an interrupt request.
1
The rising edge of INT0 or INT1 generates an interrupt request.
Bit
76543
210
INT1
INT0
PCIE1
PCIE0
–––GIMSK
Read/Write
R/W
R/w
R
Initial Value
00000
000
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